Lines Matching refs:Op
371 auto setFP16OperationAction = [&](unsigned Op, MVT VT, LegalizeAction Action,
373 setOperationAction(Op, VT, STI.allowFP16Math() ? Action : NoF16Action);
537 for (const auto &Op : {ISD::FADD, ISD::FMUL, ISD::FSUB, ISD::FMA}) {
538 setFP16OperationAction(Op, MVT::f16, Legal, Promote);
539 setFP16OperationAction(Op, MVT::v2f16, Legal, Expand);
549 for (const auto &Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FNEARBYINT, ISD::FRINT,
551 setOperationAction(Op, MVT::f16, Legal);
552 setOperationAction(Op, MVT::f32, Legal);
553 setOperationAction(Op, MVT::f64, Legal);
554 setOperationAction(Op, MVT::v2f16, Expand);
572 for (const auto &Op : {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS,
574 setOperationAction(Op, MVT::f16, Promote);
575 setOperationAction(Op, MVT::f32, Legal);
576 setOperationAction(Op, MVT::f64, Legal);
577 setOperationAction(Op, MVT::v2f16, Expand);
1251 NVPTXTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
1252 SDLoc dl(Op);
1253 const GlobalAddressSDNode *GAN = cast<GlobalAddressSDNode>(Op);
1255 Op = DAG.getTargetGlobalAddress(GAN->getGlobal(), dl, PtrVT);
1256 return DAG.getNode(NVPTXISD::Wrapper, dl, PtrVT, Op);
1537 NVPTXISD::NodeType Op;
1540 Op = NVPTXISD::StoreParam;
1543 Op = NVPTXISD::StoreParamV2;
1546 Op = NVPTXISD::StoreParamV4;
1561 Op, dl, DAG.getVTList(MVT::Other, MVT::Glue), StoreOperands,
1707 // Op to just print "call"
1810 NVPTXISD::NodeType Op;
1813 Op = NVPTXISD::LoadParam;
1816 Op = NVPTXISD::LoadParamV2;
1819 Op = NVPTXISD::LoadParamV4;
1829 Op, dl, DAG.getVTList(LoadVTs), LoadOperands, TheLoadType,
1890 NVPTXTargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
1891 SDNode *Node = Op.getNode();
1918 SDValue NVPTXTargetLowering::LowerBUILD_VECTOR(SDValue Op,
1920 //return Op;
1921 if (!(Op->getValueType(0) == MVT::v2f16 &&
1922 isa<ConstantFPSDNode>(Op->getOperand(0)) &&
1923 isa<ConstantFPSDNode>(Op->getOperand(1))))
1924 return Op;
1927 cast<ConstantFPSDNode>(Op->getOperand(0))->getValueAPF().bitcastToAPInt();
1929 cast<ConstantFPSDNode>(Op->getOperand(1))->getValueAPF().bitcastToAPInt();
1931 DAG.getConstant(E1.zext(32).shl(16) | E0.zext(32), SDLoc(Op), MVT::i32);
1932 return DAG.getNode(ISD::BITCAST, SDLoc(Op), MVT::v2f16, Const);
1935 SDValue NVPTXTargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
1937 SDValue Index = Op->getOperand(1);
1940 return Op;
1943 SDValue Vector = Op->getOperand(0);
1948 SDLoc dl(Op.getNode());
1962 SDValue NVPTXTargetLowering::LowerShiftRightParts(SDValue Op,
1964 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
1965 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
1967 EVT VT = Op.getValueType();
1969 SDLoc dl(Op);
1970 SDValue ShOpLo = Op.getOperand(0);
1971 SDValue ShOpHi = Op.getOperand(1);
1972 SDValue ShAmt = Op.getOperand(2);
1973 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
2023 SDValue NVPTXTargetLowering::LowerShiftLeftParts(SDValue Op,
2025 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2026 assert(Op.getOpcode() == ISD::SHL_PARTS);
2028 EVT VT = Op.getValueType();
2030 SDLoc dl(Op);
2031 SDValue ShOpLo = Op.getOperand(0);
2032 SDValue ShOpHi = Op.getOperand(1);
2033 SDValue ShAmt = Op.getOperand(2);
2078 SDValue NVPTXTargetLowering::LowerFROUND(SDValue Op, SelectionDAG &DAG) const {
2079 EVT VT = Op.getValueType();
2082 return LowerFROUND32(Op, DAG);
2085 return LowerFROUND64(Op, DAG);
2097 SDValue NVPTXTargetLowering::LowerFROUND32(SDValue Op,
2099 SDLoc SL(Op);
2100 SDValue A = Op.getOperand(0);
2101 EVT VT = Op.getValueType();
2138 SDValue NVPTXTargetLowering::LowerFROUND64(SDValue Op,
2140 SDLoc SL(Op);
2141 SDValue A = Op.getOperand(0);
2142 EVT VT = Op.getValueType();
2173 NVPTXTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
2174 switch (Op.getOpcode()) {
2180 return LowerGlobalAddress(Op, DAG);
2182 return Op;
2184 return LowerBUILD_VECTOR(Op, DAG);
2186 return Op;
2188 return LowerEXTRACT_VECTOR_ELT(Op, DAG);
2190 return LowerCONCAT_VECTORS(Op, DAG);
2192 return LowerSTORE(Op, DAG);
2194 return LowerLOAD(Op, DAG);
2196 return LowerShiftLeftParts(Op, DAG);
2199 return LowerShiftRightParts(Op, DAG);
2201 return LowerSelect(Op, DAG);
2203 return LowerFROUND(Op, DAG);
2209 SDValue NVPTXTargetLowering::LowerSelect(SDValue Op, SelectionDAG &DAG) const {
2210 SDValue Op0 = Op->getOperand(0);
2211 SDValue Op1 = Op->getOperand(1);
2212 SDValue Op2 = Op->getOperand(2);
2213 SDLoc DL(Op.getNode());
2215 assert(Op.getValueType() == MVT::i1 && "Custom lowering enabled only for i1");
2225 SDValue NVPTXTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
2226 if (Op.getValueType() == MVT::i1)
2227 return LowerLOADi1(Op, DAG);
2231 if (Op.getValueType() == MVT::v2f16) {
2232 LoadSDNode *Load = cast<LoadSDNode>(Op);
2238 return DAG.getMergeValues(Ops, SDLoc(Op));
2249 SDValue NVPTXTargetLowering::LowerLOADi1(SDValue Op, SelectionDAG &DAG) const {
2250 SDNode *Node = Op.getNode();
2267 SDValue NVPTXTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
2268 StoreSDNode *Store = cast<StoreSDNode>(Op);
2272 return LowerSTOREi1(Op, DAG);
2282 return LowerSTOREVector(Op, DAG);
2288 NVPTXTargetLowering::LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const {
2289 SDNode *N = Op.getNode();
2411 SDValue NVPTXTargetLowering::LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const {
2412 SDNode *Node = Op.getNode();
2714 NVPTXISD::NodeType Op;
2718 Op = NVPTXISD::StoreRetval;
2721 Op = NVPTXISD::StoreRetvalV2;
2724 Op = NVPTXISD::StoreRetvalV4;
2733 Chain = DAG.getMemIntrinsicNode(Op, dl, DAG.getVTList(MVT::Other),
2746 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
2751 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
4580 static bool IsMulWideOperandDemotable(SDValue Op,
4585 if (Op.getOpcode() == ISD::SIGN_EXTEND ||
4586 Op.getOpcode() == ISD::SIGN_EXTEND_INREG) {
4587 EVT OrigVT = Op.getOperand(0).getValueType();
4592 } else if (Op.getOpcode() == ISD::ZERO_EXTEND) {
4593 EVT OrigVT = Op.getOperand(0).getValueType();