Lines Matching defs:BaseOp
1062 const MachineOperand &BaseOp = MI.getOperand(1);
1063 assert(BaseOp.getSubReg() == 0);
1069 .addReg(BaseOp.getReg(), getRegState(BaseOp))
1077 const MachineOperand &BaseOp = MI.getOperand(1);
1078 assert(BaseOp.getSubReg() == 0);
1086 .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill)
1091 .addReg(BaseOp.getReg(), getRegState(BaseOp))
1100 const MachineOperand &BaseOp = MI.getOperand(0);
1101 assert(BaseOp.getSubReg() == 0);
1107 .addReg(BaseOp.getReg(), getRegState(BaseOp))
1116 const MachineOperand &BaseOp = MI.getOperand(0);
1117 assert(BaseOp.getSubReg() == 0);
1124 .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill)
1129 .addReg(BaseOp.getReg(), getRegState(BaseOp))
2944 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset,
2947 BaseOp = getBaseAndOffset(LdSt, Offset, AccessSize);
2948 return BaseOp != nullptr && BaseOp->isReg();
3183 const MachineOperand &BaseOp = MI.getOperand(BasePos);
3184 if (BaseOp.getSubReg() != 0)
3186 return &const_cast<MachineOperand&>(BaseOp);