Target/Hexagon/HexagonConstExtenders.cpp

365       ExtValue(const ExtDesc &ED) : ExtValue(ED.getOp()) {}
394     OffsetRange getOffsetRange(const ExtDesc &ED) const;
405     bool replaceInstrExact(const ExtDesc &ED, Register ExtR);
406     bool replaceInstrExpr(const ExtDesc &ED, const ExtenderInit &ExtI,
425     friend raw_ostream &operator<< (raw_ostream &OS, const ExtDesc &ED);
492   raw_ostream &operator<< (raw_ostream &OS, const HCE::ExtDesc &ED) {
493     assert(ED.OpNum != -1u);
494     const MachineBasicBlock &MBB = *ED.getOp().getParent()->getParent();
498     if (ED.Rd.Reg != 0)
499       OS << printReg(ED.Rd.Reg, &HRI, ED.Rd.Sub);
502     OS << " = " << PrintExpr(ED.Expr, HRI);
503     if (ED.IsDef)
1092 // Return the allowable deviation from the current value of the extender ED,
1093 // for which the instruction corresponding to ED can be modified without
1099 OffsetRange HCE::getOffsetRange(const ExtDesc &ED) const {
1101   // the instruction using ED will be converted to an indexed memory
1103   unsigned IdxOpc = getRegOffOpcode(ED.UseMI->getOpcode());
1113   if (!ED.UseMI->mayLoad() && !ED.UseMI->mayStore())
1143   ExtDesc ED;
1144   ED.OpNum = OpNum;
1163         ED.Rd = MI.getOperand(OpNum-1);
1164         ED.IsDef = true;
1171           ED.Expr.Rs = MI.getOperand(OpNum-1);
1174         ED.Expr.Rs = MI.getOperand(OpNum-2);
1175         ED.Expr.S = MI.getOperand(OpNum-1).getImm();
1183         ED.Rd = MI.getOperand(0);
1184         ED.IsDef = true;
1188         ED.Rd = { MI.getOperand(0).getReg(), Hexagon::isub_hi };
1189         ED.IsDef = true;
1192         ED.Rd = { MI.getOperand(0).getReg(), Hexagon::isub_lo };
1193         ED.IsDef = true;
1196         ED.Rd = MI.getOperand(0);
1197         ED.Expr.Rs = MI.getOperand(OpNum-1);
1202         ED.Expr.Rs = MI.getOperand(OpNum-1);
1205         ED.Rd = MI.getOperand(0);
1206         ED.Expr.Rs = MI.getOperand(OpNum+1);
1207         ED.Expr.Neg = true;
1210         ED.Expr.Rs = MI.getOperand(OpNum+1);
1211         ED.Expr.Neg = true;
1218   ED.UseMI = &MI;
1221   ExtRoot ER(ED.getOp());
1225   Extenders.push_back(ED);
1274     const ExtDesc &ED = Extenders[I];
1275     if (!ED.IsDef)
1277     ExtValue EV(ED);
1278     LLVM_DEBUG(dbgs() << " =" << I << ". " << EV << "  " << ED << '\n');
1279     assert(ED.Rd.Reg != 0);
1280     Ranges[I-Begin] = getOffsetRange(ED.Rd).shift(EV.Offset);
1285     if (ED.UseMI->getOpcode() == Hexagon::A2_tfrsi) {
1294     const ExtDesc &ED = Extenders[I];
1295     if (ED.IsDef)
1297     ExtValue EV(ED);
1298     LLVM_DEBUG(dbgs() << "  " << I << ". " << EV << "  " << ED << '\n');
1299     OffsetRange Dev = getOffsetRange(ED);
1464       const ExtDesc &ED = Extenders[I];
1465       return ED.Expr.Rs.isSlot() == IsStack &&
1466              ExtValue(ED).Offset == EV.Offset;
1494     const ExtDesc &ED = Extenders[Refs[i]];
1495     MachineBasicBlock *MBB = ED.UseMI->getParent();
1496     RefMIs.insert(ED.UseMI);
1584 bool HCE::replaceInstrExact(const ExtDesc &ED, Register ExtR) {
1585   MachineInstr &MI = *ED.UseMI;
1629     unsigned RegN = ED.OpNum;
1700 // Replace the extender ED with a form corresponding to the initializer ExtI.
1701 bool HCE::replaceInstrExpr(const ExtDesc &ED, const ExtenderInit &ExtI,
1703   MachineInstr &MI = *ED.UseMI;
1832   const ExtDesc &ED = Extenders[Idx];
1833   assert((!ED.IsDef || ED.Rd.Reg != 0) && "Missing Rd for def");
1835   assert(ExtRoot(ExtValue(ED)) == ExtRoot(DefV) && "Extender root mismatch");
1838   ExtValue EV(ED);
1840   const MachineInstr &MI = *ED.UseMI;
1854   // If ED is a def, and Diff is not 0, then all uses of the register Rd
1855   // defined by ED must be in the form (Rd, imm), i.e. the immediate offset
1858   if (ED.IsDef && Diff != 0) {
1859     for (MachineOperand &Op : MRI->use_operands(ED.Rd.Reg)) {
1868     Replaced = replaceInstrExact(ED, ExtR);
1870     Replaced = replaceInstrExpr(ED, ExtI, ExtR, Diff);
1872   if (Diff != 0 && Replaced && ED.IsDef) {
1886       assert(ED.Rd.Sub == 0 && ExtR.Sub == 0);
1887       MRI->replaceRegWith(ED.Rd.Reg, ExtR.Reg);