Target/ARM/ARMISelDAGToDAG.cpp

298   SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
299   SDNode *createSRegPairNode(EVT VT, SDValue V0, SDValue V1);
300   SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
301   SDNode *createQRegPairNode(EVT VT, SDValue V0, SDValue V1);
304   SDNode *createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
305   SDNode *createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
306   SDNode *createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
1776 SDNode *ARMDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) {
1777   SDLoc dl(V0.getNode());
1782   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1787 SDNode *ARMDAGToDAGISel::createSRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1788   SDLoc dl(V0.getNode());
1793   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1798 SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1799   SDLoc dl(V0.getNode());
1804   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1809 SDNode *ARMDAGToDAGISel::createQRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1810   SDLoc dl(V0.getNode());
1815   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1820 SDNode *ARMDAGToDAGISel::createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1,
1822   SDLoc dl(V0.getNode());
1829   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1835 SDNode *ARMDAGToDAGISel::createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1,
1837   SDLoc dl(V0.getNode());
1844   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1850 SDNode *ARMDAGToDAGISel::createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1,
1852   SDLoc dl(V0.getNode());
1859   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
2205       SDValue V0 = N->getOperand(Vec0Idx + 0);
2208         SrcReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0);
2216         SrcReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
2261   SDValue V0 = N->getOperand(Vec0Idx + 0);
2267   SDValue RegSeq = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);
2378   SDValue V0 = N->getOperand(Vec0Idx + 0);
2382       SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0);
2384       SuperReg = SDValue(createQRegPairNode(MVT::v4i64, V0, V1), 0);
2391       SuperReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
2393       SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);
4956     SDValue V0 = N->getOperand(i+1);
4958     unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg();