Lines Matching refs:State

23                           CCState &State, bool CanFail) {
27 if (unsigned Reg = State.AllocateReg(RegList))
28 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
35 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
36 State.AllocateStack(8, 4),
42 if (unsigned Reg = State.AllocateReg(RegList))
43 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
45 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
46 State.AllocateStack(4, 4),
54 CCState &State) {
55 if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
58 !f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
66 CCState &State, bool CanFail) {
72 unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList);
76 Reg = State.AllocateReg(GPRArgRegs);
84 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
85 State.AllocateStack(8, 8),
95 unsigned T = State.AllocateReg(LoRegList[i]);
99 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
100 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
108 CCState &State) {
109 if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
112 !f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
118 CCValAssign::LocInfo LocInfo, CCState &State) {
122 unsigned Reg = State.AllocateReg(HiRegList, LoRegList);
131 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
132 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
140 CCState &State) {
141 if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
143 if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
151 CCState &State) {
153 State);
176 CCState &State) {
177 SmallVectorImpl<CCValAssign> &PendingMembers = State.getPendingLocs();
195 auto &DL = State.getMachineFunction().getDataLayout();
203 unsigned RegIdx = State.getFirstUnallocated(RegList);
209 State.AllocateReg(RegList[RegIdx++]);
230 unsigned RegResult = State.AllocateRegBlock(RegList, PendingMembers.size());
235 State.addLoc(*It);
244 if (LocVT == MVT::i32 && State.getNextStackOffset() == 0) {
247 unsigned RegIdx = State.getFirstUnallocated(RegList);
250 It.convertToMem(State.AllocateStack(Size, Size));
252 It.convertToReg(State.AllocateReg(RegList[RegIdx++]));
254 State.addLoc(It);
263 State.AllocateReg(Reg);
271 It.convertToMem(State.AllocateStack(Size, Align));
272 State.addLoc(It);