Target/ARM/ARMBaseInstrInfo.cpp

2466     unsigned CurReg = RegClass->getRegister(CurRegEnc);
2473       RegList.push_back(MachineOperand::CreateReg(CurReg, false, false,
2483     if (isCalleeSavedRegister(CurReg, CSRegs) ||
2484         MI->getParent()->computeRegisterLiveness(TRI, CurReg, MI) !=
2495     RegList.push_back(MachineOperand::CreateReg(CurReg, true, false, false,
5074       unsigned CurReg = SrcLane == 1 && DstLane == 1 ? DSrc : DDst;
5075       bool CurUndef = !MI.readsRegister(CurReg, TRI);
5076       NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
5078       CurReg = SrcLane == 0 && DstLane == 0 ? DSrc : DDst;
5079       CurUndef = !MI.readsRegister(CurReg, TRI);
5080       NewMIB.addReg(CurReg, getUndefRegState(CurUndef))
5092       CurReg = SrcLane == 1 && DstLane == 0 ? DSrc : DDst;
5093       CurUndef = CurReg == DSrc && !MI.readsRegister(CurReg, TRI);
5094       MIB.addReg(CurReg, getUndefRegState(CurUndef));
5096       CurReg = SrcLane == 0 && DstLane == 1 ? DSrc : DDst;
5097       CurUndef = CurReg == DSrc && !MI.readsRegister(CurReg, TRI);
5098       MIB.addReg(CurReg, getUndefRegState(CurUndef))