Target/AMDGPU/SIMachineScheduler.h

27 #include <vector>
65   std::vector<SUnit*> SUnits;
67   std::vector<SUnit*> TopReadySUs;
68   std::vector<SUnit*> ScheduledSUnits;
78   std::vector<unsigned> InternalAdditionnalPressure;
80   std::vector<unsigned> LiveInPressure;
81   std::vector<unsigned> LiveOutPressure;
93   std::vector<unsigned> HasLowLatencyNonWaitedParent;
98   std::vector<SIScheduleBlock*> Preds;  // All blocks predecessors.
100   std::vector<std::pair<SIScheduleBlock*, SIScheduleBlockLinkKind>> Succs;
122   const std::vector<SIScheduleBlock*>& getPreds() const { return Preds; }
145   std::vector<SUnit*> getScheduledUnits() { return ScheduledSUnits; }
159   std::vector<unsigned> &getInternalAdditionnalRegUsage() {
214   std::vector<SIScheduleBlock*> Blocks;
215   std::vector<int> TopDownIndex2Block;
216   std::vector<int> TopDownBlock2Index;
228   std::vector<std::unique_ptr<SIScheduleBlock>> BlockPtrs;
231   std::vector<SIScheduleBlock*> CurrentBlocks;
232   std::vector<int> Node2CurrentBlock;
236   std::vector<int> TopDownIndex2Block;
237   std::vector<int> TopDownBlock2Index;
238   std::vector<int> BottomUpIndex2Block;
245   std::vector<int> CurrentColoring;
246   std::vector<int> CurrentTopDownReservedDependencyColoring;
247   std::vector<int> CurrentBottomUpReservedDependencyColoring;
324   std::vector<SIScheduleBlock*> Blocks;
326   std::vector<std::map<unsigned, unsigned>> LiveOutRegsNumUsages;
331   std::vector<unsigned> LastPosHighLatencyParentScheduled;
334   std::vector<SIScheduleBlock*> BlocksScheduled;
336   std::vector<SIScheduleBlock*> ReadyBlocks;
345   std::vector<unsigned> BlockNumPredsLeft;
346   std::vector<unsigned> BlockNumSuccsLeft;
354   std::vector<SIScheduleBlock*> getBlocks() { return BlocksScheduled; }
402   std::vector<int> checkRegUsageImpact(std::set<unsigned> &InRegs,
409   std::vector<unsigned> SUs;
432   std::vector<SUnit> SUnitsLinksBackup;
435   std::vector<unsigned> ScheduledSUnits;
436   std::vector<unsigned> ScheduledSUnitsInv;
497   std::vector<unsigned> IsLowLatencySU;
498   std::vector<unsigned> LowLatencyOffset;
499   std::vector<unsigned> IsHighLatencySU;
502   std::vector<int> TopDownIndex2SU;
503   std::vector<int> BottomUpIndex2SU;