Target/AMDGPU/SILoadStoreOptimizer.cpp

120     unsigned Width;
506   Width = getOpcodeWidth(*I, TII);
755     if (getBufferFormatWithCompCount(CI.Format, CI.Width + Paired.Width, STI) == 0)
766     return (EltOffset0 + CI.Width == EltOffset1 ||
767             EltOffset1 + Paired.Width == EltOffset0) &&
812   const unsigned Width = (CI.Width + Paired.Width);
815     return (Width <= 4) && (STM.hasDwordx3LoadStores() || (Width != 3));
817     switch (Width) {
1304       getBufferFormatWithCompCount(CI.Format, CI.Width + Paired.Width, *STI);
1383       getBufferFormatWithCompCount(CI.Format, CI.Width + Paired.Width, *STI);
1415   const unsigned Width = CI.Width + Paired.Width;
1422                                   Width);
1426                                   Width);
1431     switch (Width) {
1440     assert("No overlaps" && (countPopulation(CI.DMask | Paired.DMask) == Width));
1441     return AMDGPU::getMaskedMIMGOp(CI.I->getOpcode(), Width);
1448   if (CI.Width == 0 || Paired.Width == 0 || CI.Width + Paired.Width > 4)
1453     assert((countPopulation(CI.DMask | Paired.DMask) == CI.Width + Paired.Width) &&
1468   assert(CI.Width >= 1 && CI.Width <= 3);
1469   assert(Paired.Width >= 1 && Paired.Width <= 3);
1472     Idx1 = Idxs[0][Paired.Width - 1];
1473     Idx0 = Idxs[Paired.Width][CI.Width - 1];
1475     Idx0 = Idxs[0][CI.Width - 1];
1476     Idx1 = Idxs[CI.Width][Paired.Width - 1];
1486     switch (CI.Width + Paired.Width) {
1499     switch (CI.Width + Paired.Width) {
2010       OptimizeListAgain |= (CI.Width + Paired.Width) < 16;
2016       OptimizeListAgain |= (CI.Width + Paired.Width) < 4;
2022       OptimizeListAgain |= (CI.Width + Paired.Width) < 4;
2028       OptimizeListAgain |= (CI.Width + Paired.Width) < 4;
2034       OptimizeListAgain |= (CI.Width + Paired.Width) < 4;
2040       OptimizeListAgain |= (CI.Width + Paired.Width) < 4;