Target/AMDGPU/SIInstrInfo.cpp

1631                                       MachineOperand &Src0,
1690   MachineOperand &Src0 = MI.getOperand(Src0Idx);
1694   if (Src0.isReg() && Src1.isReg()) {
1695     if (isOperandLegal(MI, Src1Idx, &Src0)) {
1701   } else if (Src0.isReg() && !Src1.isReg()) {
1704     CommutedMI = swapRegAndNonRegOperand(MI, Src0, Src1);
1705   } else if (!Src0.isReg() && Src1.isReg()) {
1706     if (isOperandLegal(MI, Src1Idx, &Src0))
1707       CommutedMI = swapRegAndNonRegOperand(MI, Src1, Src0);
1714     swapSourceModifiers(MI, Src0, AMDGPU::OpName::src0_modifiers,
2367     MachineOperand *Src0 = getNamedOperand(UseMI, AMDGPU::OpName::src0);
2370     if (isInlineConstant(UseMI, *Src0, *ImmOp))
2382     if (Src0->isReg() && Src0->getReg() == Reg) {
2410       Src0->setReg(Src1Reg);
2411       Src0->setSubReg(Src1SubReg);
2412       Src0->setIsKill(Src1->isKill());
2438       if (Src0->isReg()) {
2442         MachineInstr *Def = MRI->getUniqueVRegDef(Src0->getReg());
2445           MRI->hasOneUse(Src0->getReg())) {
2446           Src0->ChangeToImmediate(Def->getOperand(1).getImm());
2448         } else if ((Register::isPhysicalRegister(Src0->getReg()) &&
2450                      RI.isSGPRClass(RI.getPhysRegClass(Src0->getReg())))) ||
2451                    (Register::isVirtualRegister(Src0->getReg()) &&
2453                      RI.isSGPRClass(MRI->getRegClass(Src0->getReg())))))
2455           // VGPR is okay as Src0 - fallthrough
2465             Src0->ChangeToImmediate(Def->getOperand(1).getImm());
2640     const MachineOperand *Src0 = &MI.getOperand(Src0Idx);
2641     if (!Src0->isReg() && !Src0->isImm())
2644     if (Src0->isImm() && !isInlineConstant(MI, Src0Idx, *Src0))
2652   const MachineOperand *Src0 = getNamedOperand(MI, AMDGPU::OpName::src0);
2665        !Src0->isReg() ||
2666        !RI.isSGPRReg(MBB->getParent()->getRegInfo(), Src0->getReg()))) {
2674                  .add(*Src0)
2685                  .add(*Src0)
2689     if (auto Imm = getFoldableImm(Src0)) {
2709       .add(*Src0)
3525     const MachineOperand &Src0 = MI.getOperand(Src0Idx);
3528     if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
3529       if (!compareMachineOp(Src0, Src1) &&
3530           !compareMachineOp(Src0, Src2)) {
3538     const MachineOperand &Src0 = MI.getOperand(Src0Idx);
3542     if (!Src0.isReg() &&
3543         !isInlineConstant(Src0, Desc.OpInfo[Src0Idx].OperandType))
3612     const MachineOperand &Src0 = MI.getOperand(Src0Idx);
3616         !isSubRegOf(RI, ImpUse, IsDst ? *Dst : Src0)) {
4027   MachineOperand &Src0 = MI.getOperand(Src0Idx);
4036       Src0.isReg() && (RI.isSGPRReg(MRI, Src0.getReg()) ||
4037        isLiteralConstantLike(Src0, InstrDesc.OpInfo[Src0Idx])))
4045     if (Src0.isReg() && RI.isVGPR(MRI, Src0.getReg())) {
4048           .add(Src0);
4049       Src0.ChangeToRegister(Reg, false);
4062   if (Src0.isReg() && RI.isAGPR(MRI, Src0.getReg()))
4101       !isLegalRegOperand(MRI, InstrDesc.OpInfo[Src1Idx], Src0)) {
4114   Register Src0Reg = Src0.getReg();
4115   unsigned Src0SubReg = Src0.getSubReg();
4116   bool Src0Kill = Src0.isKill();
4119     Src0.ChangeToImmediate(Src1.getImm());
4121     Src0.ChangeToRegister(Src1.getReg(), false, false, Src1.isKill());
4122     Src0.setSubReg(Src1.getSubReg());
4633     Register Src0 = MI.getOperand(1).getReg();
4635     const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
5180   MachineOperand &Src0 = Inst.getOperand(1);
5185     legalizeGenericOperand(MBB, MII, &AMDGPU::VGPR_32RegClass, Src0, MRI, DL);
5189       .add(Src0)
5199     bool Src0IsSGPR = Src0.isReg() &&
5200                       RI.isSGPRClass(MRI.getRegClass(Src0.getReg()));
5211       BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), Temp).add(Src0);
5218       .add(Src0)
5222         .add(Src0)
5246   MachineOperand &Src0 = Inst.getOperand(1);
5253     .add(Src0)
5275   MachineOperand &Src0 = Inst.getOperand(1);
5285     .add(Src0)
5302   MachineOperand &Src0 = Inst.getOperand(1);
5308   const TargetRegisterClass *Src0RC = Src0.isReg() ?
5309     MRI.getRegClass(Src0.getReg()) :
5314   MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
5324   MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
5366   MachineOperand &Src0 = Inst.getOperand(1);
5371   const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0.getReg());
5376   MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
5382   MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
5428   MachineOperand &Src0 = Inst.getOperand(1);
5435   const TargetRegisterClass *Src0RC = Src0.isReg() ?
5436     MRI.getRegClass(Src0.getReg()) :
5446   MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
5450   MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
5492   MachineOperand &Src0 = Inst.getOperand(1);
5505   if (Src0.isReg() && RI.isSGPRReg(MRI, Src0.getReg())) {
5506     Op0 = &Src0;
5510     Op1 = &Src0;
5666   MachineOperand &Src0 = Inst.getOperand(1);
5682       .add(Src0);
5696       .add(Src0)
5705       .add(Src0);