Target/AMDGPU/SIInstrInfo.cpp

875       MachineOperand RegOp = Cond[1];
876       RegOp.setImplicit(false);
879         .add(RegOp);
889       MachineOperand RegOp = Cond[1];
890       RegOp.setImplicit(false);
893         .add(RegOp);
1652                                              MachineOperand &RegOp,
1654   Register Reg = RegOp.getReg();
1655   unsigned SubReg = RegOp.getSubReg();
1656   bool IsKill = RegOp.isKill();
1657   bool IsDead = RegOp.isDead();
1658   bool IsUndef = RegOp.isUndef();
1659   bool IsDebug = RegOp.isDebug();
1662     RegOp.ChangeToImmediate(NonRegOp.getImm());
1664     RegOp.ChangeToFrameIndex(NonRegOp.getIndex());
6419       auto &RegOp = MI.getOperand(1 + 2 * I);
6420       return getRegOrUndef(RegOp);