Target/AMDGPU/SIISelLowering.cpp

3613     MachineOperand &Src0 = MI.getOperand(1);
3620      Src0, BoolRC, AMDGPU::sub0,
3623       Src0, BoolRC, AMDGPU::sub1,
3760     Register Src0 = MI.getOperand(1).getReg();
3774       .addReg(Src0, 0, AMDGPU::sub0)
3780       .addReg(Src0, 0, AMDGPU::sub1)
4250   SDValue Src0 = N->getOperand(1);
4252   EVT CmpVT = Src0.getValueType();
4256     Src0 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src0);
4264   SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, SL, CCVT, Src0,
4289       SDValue Src0 = N->getOperand(1);
4293                                 Src0, Src1);
4301       SDValue Src0 = N->getOperand(1);
4317         Results.push_back(DAG.getNode(Opcode, SL, VT, Src0, Src1));
4319         SDValue Cvt = DAG.getNode(Opcode, SL, MVT::i32, Src0, Src1);
5925         Op.getOperand(1), // Src0
5939         Op.getOperand(1), // Src0
6007     SDValue Src0 = Param->isAllOnesValue() ? Numerator : Denominator;
6009     return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0,
6820     SDValue Src0 = Op.getOperand(4);
6830       DAG.getNode(ISD::BITCAST, DL, MVT::f32, Src0),
7641   SDValue Src0 = Op.getOperand(0);
7644   SDValue CvtSrc0 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src0);
7653   return DAG.getNode(AMDGPUISD::DIV_FIXUP, SL, MVT::f16, BestQuot, Src1, Src0);
9234   SDValue Src0 = N->getOperand(0);
9238   if (isClampZeroToOne(Src0, Src1)) {
9253     if (isa<ConstantFPSDNode>(Src0) && !isa<ConstantFPSDNode>(Src1))
9254       std::swap(Src0, Src1);
9259     if (isa<ConstantFPSDNode>(Src0) && !isa<ConstantFPSDNode>(Src1))
9260       std::swap(Src0, Src1);
9263       return DAG.getNode(AMDGPUISD::CLAMP, SL, VT, Src0);
9271   SDValue Src0 = N->getOperand(0);
9273   if (Src0.isUndef() && Src1.isUndef())
10365     SDValue Src0 = Node->getOperand(0);
10369     if ((Src0.isMachineOpcode() &&
10370          Src0.getMachineOpcode() != AMDGPU::IMPLICIT_DEF) &&
10371         (Src0 == Src1 || Src0 == Src2))
10374     MVT VT = Src0.getValueType().getSimpleVT();
10376         getRegClassFor(VT, Src0.getNode()->isDivergent());
10382                                       UndefReg, Src0, SDValue());
10386     if (Src0.isMachineOpcode() &&
10387         Src0.getMachineOpcode() == AMDGPU::IMPLICIT_DEF) {
10390         Src0 = Src1;
10393         Src0 = Src2;
10396         Src0 = UndefReg;
10402     SmallVector<SDValue, 4> Ops = { Src0, Src1, Src2 };