AMDGPU/AsmParser/AMDGPUAsmParser.cpp

899     auto Op = std::make_unique<AMDGPUOperand>(Immediate, AsmParser);
900     Op->Imm.Val = Val;
901     Op->Imm.IsFPImm = IsFPImm;
902     Op->Imm.Type = Type;
903     Op->Imm.Mods = Modifiers();
904     Op->StartLoc = Loc;
905     Op->EndLoc = Loc;
906     return Op;
923     auto Op = std::make_unique<AMDGPUOperand>(Register, AsmParser);
924     Op->Reg.RegNo = RegNo;
925     Op->Reg.Mods = Modifiers();
926     Op->StartLoc = S;
927     Op->EndLoc = E;
928     return Op;
933     auto Op = std::make_unique<AMDGPUOperand>(Expression, AsmParser);
934     Op->Expr = Expr;
935     Op->StartLoc = S;
936     Op->EndLoc = S;
937     return Op;
1232   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
1299   bool parseSendMsgBody(OperandInfoTy &Msg, OperandInfoTy &Op, OperandInfoTy &Stream);
1301                        const OperandInfoTy &Op,
1366   bool parseSwizzleOperands(const unsigned OpNum, int64_t* Op,
2583     AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands.back());
2584     if (Op.isExpr()) {
2585       Error(Op.getStartLoc(), "expected an absolute expression");
2588     Op.setModifiers(Mods);
2617     AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands.back());
2618     if (Op.isExpr()) {
2619       Error(Op.getStartLoc(), "expected an absolute expression");
2622     Op.setModifiers(Mods);
2678     const auto &Op = Inst.getOperand(OpNum);
2679     if (!Op.isImm() || Op.getImm() != AMDGPU::SDWA::SdwaSel::DWORD) {
3291     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
3292     if (Op.isFlatOffset())
3293       return Op.getStartLoc();
3308   const auto &Op = Inst.getOperand(OpNum);
3309   if (!hasFlatOffsets() && Op.getImm() != 0) {
3320     if (!isIntN(OffsetSize, Op.getImm())) {
3327     if (!isUIntN(OffsetSize - 1, Op.getImm())) {
4612     int64_t Op;
4614     if (!parseExpr(Op))
4617     if (Op != 0 && Op != 1) {
4622     Val |= (Op << I);
4773     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
4776     if (Op.isReg()) {
4777       Op.addRegOperands(Inst, 1);
4782     OptionalIdx[Op.getImmTy()] = i;
4797     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
4800     if (Op.isReg()) {
4801       Op.addRegOperands(Inst, 1);
4805     if (Op.isToken() && Op.getToken() == "gds") {
4811     OptionalIdx[Op.getImmTy()] = i;
4836     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
4839     if (Op.isReg()) {
4842       Op.addRegOperands(Inst, 1);
4847     if (Op.isOff()) {
4855     if (Op.isImm() && Op.getImmTy() == AMDGPUOperand::ImmTyExpTgt) {
4856       Op.addImmOperands(Inst, 1);
4860     if (Op.isToken() && Op.getToken() == "done")
4864     OptionalIdx[Op.getImmTy()] = i;
5077                                   OperandInfoTy &Op,
5089     Op.IsDefined = true;
5091         (Op.Id = getMsgOpId(Msg.Id, getTokenStr())) >= 0) {
5093     } else if (!parseExpr(Op.Id)) {
5109                                  const OperandInfoTy &Op,
5122   } else if (Strict && (msgRequiresOp(Msg.Id) != Op.IsDefined)) {
5123     Error(S, Op.IsDefined ?
5127   } else if (!isValidMsgOp(Msg.Id, Op.Id, Strict)) {
5130   } else if (Strict && !msgSupportsStream(Msg.Id, Op.Id) && Stream.IsDefined) {
5133   } else if (!isValidMsgStream(Msg.Id, Op.Id, Stream.Id, Strict)) {
5151     OperandInfoTy Op(OP_NONE_);
5153     if (parseSendMsgBody(Msg, Op, Stream) &&
5154         validateSendMsg(Msg, Op, Stream, Loc)) {
5155       ImmVal = encodeMsg(Msg.Id, Op.Id, Stream.Id);
5470 AMDGPUAsmParser::parseSwizzleOperands(const unsigned OpNum, int64_t* Op,
5479     if (!parseExpr(Op[i])) {
5482     if (Op[i] < MinVal || Op[i] > MaxVal) {
5845     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
5848     if (Op.isReg()) {
5849       Op.addRegOperands(Inst, 1);
5854         Op.addRegOperands(Inst, 1);
5859     if (Op.isImm() && Op.getImmTy() == AMDGPUOperand::ImmTyNone) {
5860       Op.addImmOperands(Inst, 1);
5864     HasLdsModifier |= Op.isLDS();
5868     if (Op.isToken()) {
5871     assert(Op.isImm());
5874     OptionalIdx[Op.getImmTy()] = i;
5910     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
5913     if (Op.isReg()) {
5914       Op.addRegOperands(Inst, 1);
5919     if (Op.isImm() && Op.getImmTy() == AMDGPUOperand::ImmTyNone) {
5920       Op.addImmOperands(Inst, 1);
5926     if (Op.isToken()) {
5929     assert(Op.isImm());
5932     OptionalIdx[Op.getImmTy()] = i;
5967     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
5970     if (Op.isReg()) {
5971       Op.addRegOperands(Inst, 1);
5972     } else if (Op.isImmModifier()) {
5973       OptionalIdx[Op.getImmTy()] = I;
5974     } else if (!Op.isToken()) {
6152   for (const OptionalOperand &Op : AMDGPUOptionalOperandTable) {
6154     if (Op.IsBit) {
6155       res = parseNamedBit(Op.Name, Operands, Op.Type);
6156     } else if (Op.Type == AMDGPUOperand::ImmTyOModSI) {
6158     } else if (Op.Type == AMDGPUOperand::ImmTySdwaDstSel ||
6159                Op.Type == AMDGPUOperand::ImmTySdwaSrc0Sel ||
6160                Op.Type == AMDGPUOperand::ImmTySdwaSrc1Sel) {
6161       res = parseSDWASel(Operands, Op.Name, Op.Type);
6162     } else if (Op.Type == AMDGPUOperand::ImmTySdwaDstUnused) {
6164     } else if (Op.Type == AMDGPUOperand::ImmTyOpSel ||
6165                Op.Type == AMDGPUOperand::ImmTyOpSelHi ||
6166                Op.Type == AMDGPUOperand::ImmTyNegLo ||
6167                Op.Type == AMDGPUOperand::ImmTyNegHi) {
6168       res = parseOperandArrayWithPrefix(Op.Name, Operands, Op.Type,
6169                                         Op.ConvertResult);
6170     } else if (Op.Type == AMDGPUOperand::ImmTyDim) {
6172     } else if (Op.Type == AMDGPUOperand::ImmTyFORMAT && !isGFX10()) {
6175       res = parseIntWithPrefix(Op.Name, Operands, Op.Type, Op.ConvertResult);
6246     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
6248       Op.addRegOrImmWithFPInputModsOperands(Inst, 2);
6249     } else if (Op.isInterpSlot() ||
6250                Op.isInterpAttr() ||
6251                Op.isAttrChan()) {
6252       Inst.addOperand(MCOperand::createImm(Op.getImm()));
6253     } else if (Op.isImmModifier()) {
6254       OptionalIdx[Op.getImmTy()] = I;
6286       AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
6288         Op.addRegOrImmWithFPInputModsOperands(Inst, 2);
6289       } else if (Op.isImmModifier()) {
6290         OptionalIdx[Op.getImmTy()] = I;
6291       } else if (Op.isRegOrImm()) {
6292         Op.addRegOrImmOperands(Inst, 1);
6300       AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
6301       if (Op.isMod()) {
6302         OptionalIdx[Op.getImmTy()] = I;
6304         Op.addRegOrImmOperands(Inst, 1);
6736     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
6738     if (Op.isReg() && validateVccOperand(Op.getReg())) {
6745       if (Op.isDPP8()) {
6746         Op.addImmOperands(Inst, 1);
6748         Op.addRegWithFPInputModsOperands(Inst, 2);
6749       } else if (Op.isFI()) {
6750         Fi = Op.getImm();
6751       } else if (Op.isReg()) {
6752         Op.addRegOperands(Inst, 1);
6758         Op.addRegWithFPInputModsOperands(Inst, 2);
6759       } else if (Op.isDPPCtrl()) {
6760         Op.addImmOperands(Inst, 1);
6761       } else if (Op.isImm()) {
6763         OptionalIdx[Op.getImmTy()] = I;
6887     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
6888     if (SkipVcc && !SkippedVcc && Op.isReg() &&
6889         (Op.getReg() == AMDGPU::VCC || Op.getReg() == AMDGPU::VCC_LO)) {
6907       Op.addRegOrImmWithInputModsOperands(Inst, 2);
6908     } else if (Op.isImm()) {
6910       OptionalIdx[Op.getImmTy()] = I;
6995 unsigned AMDGPUAsmParser::validateTargetOperandClass(MCParsedAsmOperand &Op,
7001   AMDGPUOperand &Operand = (AMDGPUOperand&)Op;