Target/AMDGPU/AMDGPURegisterBankInfo.cpp

71         const LLT S32 = LLT::scalar(32);
73         assert(MRI.getType(DstReg) == S32);
79         auto True = B.buildConstant(S32, Opc == AMDGPU::G_SEXT ? -1 : 1);
80         auto False = B.buildConstant(S32, 0);
882           LLT S32 = LLT::scalar(32);
909               Register CurrentLaneOpRegLo = MRI.createGenericVirtualRegister(S32);
910               Register CurrentLaneOpRegHi = MRI.createGenericVirtualRegister(S32);
943               CurrentLaneOpReg = MRI.createGenericVirtualRegister(S32);
1276   const LLT S32 = LLT::scalar(32);
1279   return B.buildMerge(LLT::vector(NumElts, S32), WideRegs).getReg(0);
1302   const LLT S32 = LLT::scalar(32);
1326         BaseReg = B.buildConstant(S32, Overflow).getReg(0);
1328         auto OverflowVal = B.buildConstant(S32, Overflow);
1329         BaseReg = B.buildAdd(S32, BaseReg, OverflowVal).getReg(0);
1335     BaseReg = B.buildConstant(S32, 0).getReg(0);
1480     const LLT S32 = LLT::scalar(32);
1519     if (Helper.widenScalar(MI, 0, S32) != LegalizerHelper::Legalized)
1543     const LLT S32 = LLT::scalar(32);
1544     Register NewDstReg = MRI.createGenericVirtualRegister(S32);
1550       Register NewSrcReg = MRI.createGenericVirtualRegister(S32);
1575       const LLT S32 = LLT::scalar(32);
1576       Register NewCondReg = MRI.createGenericVirtualRegister(S32);
1627       const LLT S32 = LLT::scalar(32);
1628       Register NewCondReg = MRI.createGenericVirtualRegister(S32);
1753     LLT S32 = LLT::scalar(32);
1762       if (Helper.widenScalar(MI, 0, S32) != LegalizerHelper::Legalized)
1791       const LLT S32 = LLT::scalar(32);
1800         auto ShiftAmt = B.buildConstant(S32, 31);
1889     const LLT S32 = LLT::scalar(32);
1900       ZextLo = B.buildZExt(S32, Lo).getReg(0);
1903       Register ZextHi = B.buildZExt(S32, Hi).getReg(0);
1906       auto ShiftAmt = B.buildConstant(S32, 16);
1909       ShiftHi = B.buildShl(S32, ZextHi, ShiftAmt).getReg(0);
1912       Register MaskLo = B.buildConstant(S32, 0xffff).getReg(0);
1915       auto ShiftAmt = B.buildConstant(S32, 16);
1918       ShiftHi = B.buildShl(S32, Hi, ShiftAmt).getReg(0);
1921       ZextLo = B.buildAnd(S32, Lo, MaskLo).getReg(0);
1925     auto Or = B.buildOr(S32, ZextLo, ShiftHi);
1978     const LLT S32 = LLT::scalar(32);
1982     auto One = B.buildConstant(S32, 1);
1991     auto IdxLo = B.buildShl(S32, IdxReg, One);
1992     auto IdxHi = B.buildAdd(S32, IdxLo, One);
2018       Register TmpReg0 = MRI.createGenericVirtualRegister(S32);
2019       Register TmpReg1 = MRI.createGenericVirtualRegister(S32);
2057     const LLT S32 = LLT::scalar(32);
2062     auto One = B.buildConstant(S32, 1);
2071     auto IdxLo = B.buildShl(S32, IdxReg, One);
2072     auto IdxHi = B.buildAdd(S32, IdxLo, One);