lib/CodeGen/MachinePipeliner.cpp

1011 /// for each cycle that is required. When adding a new instruction, we attempt
1042     // DFA is needed for each cycle.
1337     // Add the artificial dependencies if it does not form a cycle.
2014         // When scheduling a Phi it is better to start at the late cycle and go
2299     // Add the already scheduled instructions at the specified cycle to the
2319         dbgs() << "\tinsert at cycle " << curCycle << " ";
2332       dbgs() << "\tfailed to insert at cycle " << curCycle << " ";
2339 // Return the cycle of the earliest scheduled instruction in the chain.
2362 // Return the cycle of the latest scheduled instruction in the chain.
2405   for (int cycle = getFirstCycle(); cycle <= LastCycle; ++cycle) {
2407     // Iterate over each instruction in the current cycle.
2408     for (SUnit *I : getInstructions(cycle)) {
2415             int EarlyStart = cycle + Dep.getLatency() -
2423             int LateStart = cycle - Dep.getLatency() +
2433           *MinLateStart = std::min(*MinLateStart, cycle);
2439             int LateStart = cycle - Dep.getLatency() +
2447             int EarlyStart = cycle + Dep.getLatency() -
2457 /// Order the instructions within a cycle so that the definitions occur
2537       // so may have nodes in same cycle with Anti denpendent on HW regs.
2769       // same cycle but occurs later in the serialized order.
2812   for (int cycle = getFirstCycle(); cycle <= getFinalCycle(); ++cycle) {
2816           ScheduledInstrs[cycle + (stage * InitiationInterval)];
2820         ScheduledInstrs[cycle].push_front(*I);
2826   for (int cycle = getFinalCycle() + 1; cycle <= LastCycle; ++cycle)
2827     ScheduledInstrs.erase(cycle);
2836   // Reorder the instructions in each cycle to fix and improve the
2872   // Iterate over each cycle.
2873   for (int cycle = getFirstCycle(); cycle <= getFinalCycle(); ++cycle) {
2874     // Iterate over each instruction in the cycle.
2875     const_sched_iterator cycleInstrs = ScheduledInstrs.find(cycle);
2877       os << "cycle " << cycle << " (" << stageScheduled(CI) << ") ";