Lines Matching defs:DImode
978 if (GET_CODE (operands[1]) == LABEL_REF && mode == DImode)
1047 case DImode:
1101 /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
1117 temp = gen_rtx_REG (DImode, REGNO (temp));
1137 temp1 = gen_reg_rtx (DImode);
1139 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1140 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
1164 temp1 = gen_reg_rtx (DImode);
1165 temp2 = gen_reg_rtx (DImode);
1166 temp3 = gen_reg_rtx (DImode);
1172 gen_rtx_ASHIFT (DImode, temp2, GEN_INT (12))));
1199 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
1209 temp1 = gen_reg_rtx (DImode);
1210 temp2 = gen_reg_rtx (DImode);
1211 temp3 = gen_reg_rtx (DImode);
1212 temp4 = gen_reg_rtx (DImode);
1213 temp5 = gen_reg_rtx (DImode);
1220 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
1222 gen_rtx_PLUS (DImode, temp4, temp2)));
1246 temp1 = gen_reg_rtx (DImode);
1247 temp2 = gen_reg_rtx (DImode);
1271 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
1281 temp1 = gen_reg_rtx (DImode);
1282 temp2 = gen_reg_rtx (DImode);
1283 temp3 = gen_reg_rtx (DImode);
1284 temp4 = gen_reg_rtx (DImode);
1285 temp5 = gen_reg_rtx (DImode);
1292 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
1294 gen_rtx_PLUS (DImode, temp4, temp2)));
1339 return gen_rtx_IOR (DImode, src, GEN_INT (val));
1345 return gen_rtx_XOR (DImode, src, GEN_INT (val));
1384 gen_rtx_NOT (DImode, temp)));
1424 gen_rtx_ASHIFT (DImode, temp2,
1449 sub_temp = gen_reg_rtx (DImode);
1469 rtx temp2 = gen_reg_rtx (DImode);
1470 rtx temp3 = gen_reg_rtx (DImode);
1471 rtx temp4 = gen_reg_rtx (DImode);
1474 gen_rtx_ASHIFT (DImode, sub_temp,
1483 gen_rtx_PLUS (DImode, temp4, temp3)));
1488 gen_rtx_PLUS (DImode, temp4, temp2)));
1504 gen_rtx_ASHIFT (DImode, sub_temp,
1507 gen_rtx_IOR (DImode, op0, low1)));
1518 gen_rtx_ASHIFT (DImode, sub_temp,
1521 gen_rtx_IOR (DImode, op0, low2)));
1530 gen_rtx_ASHIFT (DImode, sub_temp,
1534 gen_rtx_IOR (DImode, op0, low3)));
1685 temp = gen_reg_rtx (DImode);
1734 gen_rtx_ASHIFT (DImode,
1740 gen_rtx_LSHIFTRT (DImode,
1767 gen_rtx_LSHIFTRT (DImode, temp,
1772 gen_rtx_ASHIFT (DImode, temp,
1839 gen_rtx_NOT (DImode, temp)));
1934 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
1941 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2045 && (GET_MODE (sparc_compare_op0) == DImode
2046 || GET_MODE (operands[0]) == DImode))
2062 && GET_MODE (operands[0]) == DImode
2066 gen_rtx_IF_THEN_ELSE (DImode,
2067 gen_rtx_fmt_ee (compare_code, DImode,
2083 if (GET_MODE (op0) != DImode)
2085 temp = gen_reg_rtx (DImode);
2092 gen_rtx_fmt_ee (compare_code, DImode,
2320 case DImode:
2334 case DImode:
2348 case DImode:
2362 case DImode:
2510 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2518 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2541 /* The 'restore src1,src2,dest' pattern for DImode. */
2543 && register_operand (XEXP (src, 0), DImode)
2544 && arith_double_operand (XEXP (src, 1), DImode))
2553 && register_operand (XEXP (src, 0), DImode)
2554 && immediate_operand (XEXP (src, 1), DImode))))
2560 || register_operand (XEXP (src, 0), DImode))
2945 DFmode/DImode because then mem_min_alignment is likely to be zero
2949 && (mode == DFmode || mode == DImode))
3789 mem = gen_rtx_MEM (DImode, plus_constant (base, offset));
3793 insn = emit_move_insn (mem, gen_rtx_REG (DImode, i));
3797 emit_move_insn (gen_rtx_REG (DImode, i), mem);
3813 mode = i < 32 ? DImode : DFmode;
6091 DImode, 2,
6095 mode = DImode;
6157 /* Generate an unsigned DImode to FP conversion. This is the same code
6166 in = force_reg (DImode, operands[1]);
6169 i0 = gen_reg_rtx (DImode);
6170 i1 = gen_reg_rtx (DImode);
6173 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
6190 /* Generate an FP to unsigned DImode conversion. This is the same code
6202 i0 = gen_reg_rtx (DImode);
6203 i1 = gen_reg_rtx (DImode);
6214 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, in))));
6223 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, f0))));
6281 gcc_assert (mode == DImode);
7240 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt);
7241 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr);
7242 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp))));
7247 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
7624 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
7639 if (GET_MODE (x) == DImode)
7684 /* Returns assembly code to perform a DImode shift using
7847 set_conv_libfunc (sfix_optab, DImode, TFmode, "_Q_qtoll");
7848 set_conv_libfunc (ufix_optab, DImode, TFmode, "_Q_qtoull");
7849 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_Q_lltoq");
7850 set_conv_libfunc (ufloat_optab, TFmode, DImode, "_Q_ulltoq");
7855 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
7856 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
7857 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
7858 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
7875 set_optab_libfunc (smul_optab, DImode, "__mul64");
7876 set_optab_libfunc (sdiv_optab, DImode, "__div64");
7877 set_optab_libfunc (udiv_optab, DImode, "__udiv64");
7878 set_optab_libfunc (smod_optab, DImode, "__rem64");
7879 set_optab_libfunc (umod_optab, DImode, "__urem64");
7884 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftol");
7885 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoul");
7886 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtol");
7887 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoul");
8429 if (mode == DImode)
8455 if (mode == DImode)
8722 spill_reg = gen_rtx_REG (DImode, 15); /* %o7 */