config/ia64/ia64.c

267 static bool ia64_scalar_mode_supported_p (enum machine_mode mode);
268 static bool ia64_vector_mode_supported_p (enum machine_mode mode);
841 	enum machine_mode mode = GET_MODE (x);
843 	if (mode == V2SFmode)
846 	return (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
847 		&& GET_MODE_SIZE (mode) <= 8);
870   /* ILP32 mode still loads 64-bits of data from the GOT.  This avoids
1061   enum machine_mode mode = GET_MODE (op0);
1064     op1 = force_reg (mode, op1);
1066   if ((mode == Pmode || mode == ptr_mode) && symbolic_operand (op1, VOIDmode))
1084       if (any_offset_symbol_operand (sym, mode))
1086       else if (aligned_offset_symbol_operand (sym, mode))
1114 	  rtx subtarget = no_new_pseudos ? op0 : gen_reg_rtx (mode);
1118 	  op1 = expand_simple_binop (mode, PLUS, subtarget,
1383 spill_xfmode_rfmode_operand (rtx in, int force, enum machine_mode mode)
1391       return adjust_address (memt, mode, 0);
1395       rtx memx = assign_stack_temp (mode, 16, 0);
1408 ia64_expand_movxf_movrf (enum machine_mode mode, rtx operands[])
1452 					   0, mode));
1455 					   0, mode));
1460       if (register_operand (operands[1], mode))
1461 	operands[1] = spill_xfmode_rfmode_operand (operands[1], 1, mode);
1484       if (register_operand (operands[0], mode))
1487 	  op1 = gen_rtx_SUBREG (mode, op1, 0);
1488 	  operands[1] = spill_xfmode_rfmode_operand (op1, 0, mode);
1509       operands[1] = spill_xfmode_rfmode_operand (operands[1], 0, mode);
1515 	    in = validize_mem (force_const_mem (mode, in));
1521 	      memx = adjust_address (memt, mode, 0);
1529 	operands[1] = force_reg (mode, operands[1]);
1536    that holds the compare result in the proper mode.  */
1541 ia64_expand_compare (enum rtx_code code, enum machine_mode mode)
1615   return gen_rtx_fmt_ee (code, mode, cmp, const0_rtx);
1622 ia64_expand_vecint_compare (enum rtx_code code, enum machine_mode mode,
1663       switch (mode)
1687 	    op1 = CONST0_RTX (mode);
1694 	  x = gen_reg_rtx (mode);
1696 				  gen_rtx_US_MINUS (mode, op0, op1)));
1700 	  op1 = CONST0_RTX (mode);
1709   x = gen_rtx_fmt_ee (code, mode, op0, op1);
1720   enum machine_mode mode = GET_MODE (operands[0]);
1725   cmp = gen_reg_rtx (mode);
1726   negate = ia64_expand_vecint_compare (code, mode, cmp,
1732   if (ot == CONST0_RTX (mode))
1734       if (of == CONST0_RTX (mode))
1740       x = gen_rtx_NOT (mode, cmp);
1741       x = gen_rtx_AND (mode, x, of);
1744   else if (of == CONST0_RTX (mode))
1746       x = gen_rtx_AND (mode, cmp, ot);
1753       t = gen_reg_rtx (mode);
1754       x = gen_rtx_AND (mode, cmp, operands[1+negate]);
1757       f = gen_reg_rtx (mode);
1758       x = gen_rtx_NOT (mode, cmp);
1759       x = gen_rtx_AND (mode, x, operands[2-negate]);
1762       x = gen_rtx_IOR (mode, t, f);
1770 ia64_expand_vecint_minmax (enum rtx_code code, enum machine_mode mode,
1776   if (mode == V8QImode && (code == UMIN || code == UMAX))
1778   if (mode == V4HImode && (code == SMIN || code == SMAX))
1782   if (mode == V4HImode && code == UMAX)
1784       rtx x, tmp = gen_reg_rtx (mode);
1786       x = gen_rtx_US_MINUS (mode, operands[1], operands[2]);
1827   enum machine_mode wmode, mode;
1833   mode = GET_MODE (operands[1]);
1835   switch (mode)
1853     x = CONST0_RTX (mode);
1858       x = gen_reg_rtx (mode);
1860       neg = ia64_expand_vecint_compare (LT, mode, x, operands[1],
1861 					CONST0_RTX (mode));
1869   emit_insn (unpack_l (gen_lowpart (mode, l), operands[1], x));
1870   emit_insn (unpack_h (gen_lowpart (mode, h), operands[1], x));
2093   enum machine_mode mode = GET_MODE (mem);
2098   if ((mode == SImode || mode == DImode)
2100       && fetchadd_operand (val, mode))
2106         old_dst = gen_reg_rtx (mode);
2110       if (mode == SImode)
2118 	  new_reg = expand_simple_binop (mode, PLUS, old_dst, val, new_dst,
2134   if (mode != DImode)
2136       val = simplify_gen_subreg (DImode, val, mode, 0);
2137       emit_insn (gen_extend_insn (cmp_reg, mem, DImode, mode, 1));
2149     emit_move_insn (old_dst, gen_lowpart (mode, cmp_reg));
2160   if (mode != DImode)
2161     new_reg = gen_lowpart (mode, new_reg);
2165   switch (mode)
2656    fact with the appropriate offsets to a POST_MODIFY memory mode.
3797   /* Make sure addresses are Pmode even if we are in ILP32 mode. */
3826    for the last named argument which has type TYPE and mode MODE.
3831 ia64_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3838   ia64_function_arg_advance (&next_cum, mode, type, 1);
3849    it is, return the mode of the floating point type that appears
3864   enum machine_mode mode;
3892 	 mode if this is contained within an aggregate.  */
3909 	  mode = hfa_element_mode (TREE_TYPE (t), 1);
3912 	      if (mode != element_mode)
3915 	  else if (GET_MODE_CLASS (mode) != MODE_FLOAT)
3920 	      element_mode = mode;
3939 ia64_function_arg_words (tree type, enum machine_mode mode)
3943   if (mode == BLKmode)
3946     words = GET_MODE_SIZE (mode);
3984 ia64_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
3988   int words = ia64_function_arg_words (type, mode);
4022       byte_size = ((mode == BLKmode)
4023 		   ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
4046       /* Fill in the GR regs.  We must use DImode here, not the hfa mode.  */
4079       return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
4085   else if (mode == TFmode || mode == TCmode
4086 	   || (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS))
4088       int byte_size = ((mode == BLKmode)
4089                        ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
4091 	&& (mode == BLKmode || (type && AGGREGATE_TYPE_P (type)))
4100 	  return gen_rtx_PARALLEL (mode, gen_rtvec (1, gr_reg));
4103 	return gen_rtx_REG (mode, basereg + cum->words + offset);
4112 	return gen_rtx_REG (mode, FR_ARG_FIRST + cum->fp_regs);
4113       /* In big-endian mode, an anonymous SFmode value must be represented
4116       else if (BYTES_BIG_ENDIAN && mode == SFmode)
4117 	return gen_rtx_PARALLEL (mode,
4123 	return gen_rtx_REG (mode, basereg + cum->words + offset);
4131 	(BYTES_BIG_ENDIAN && mode == SFmode) ? DImode : mode;
4134 				      gen_rtx_REG (mode, (FR_ARG_FIRST
4143       return gen_rtx_PARALLEL (mode, gen_rtvec (2, fp_reg, gr_reg));
4152 ia64_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4155   int words = ia64_function_arg_words (type, mode);
4177 ia64_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4180   int words = ia64_function_arg_words (type, mode);
4215       byte_size = ((mode == BLKmode)
4216 		   ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
4233   else if (mode == TFmode || mode == TCmode
4234            || (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS))
4245 	cum->fp_regs += (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT ? 2 : 1);
4252       cum->fp_regs += (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT ? 2 : 1);
4262 ia64_function_arg_boundary (enum machine_mode mode, tree type)
4265   if (mode == TFmode && TARGET_HPUX && TARGET_ILP32)
4276   if (GET_MODE_BITSIZE (mode) > PARM_BOUNDARY)
4339   enum machine_mode mode;
4343   mode = TYPE_MODE (valtype);
4344   byte_size = GET_MODE_SIZE (mode);
4345   if (mode == BLKmode)
4375   enum machine_mode mode;
4378   mode = TYPE_MODE (valtype);
4390       byte_size = ((mode == BLKmode)
4391 		   ? int_size_in_bytes (valtype) : GET_MODE_SIZE (mode));
4400       return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
4402   else if (FLOAT_TYPE_P (valtype) && mode != TFmode && mode != TCmode)
4403     return gen_rtx_REG (mode, FR_ARG_FIRST);
4408       /* In big-endian mode, we need to manage the layout of aggregates
4412 	  && (mode == BLKmode || (valtype && AGGREGATE_TYPE_P (valtype))))
4420       else if (mode == XFmode || mode == XCmode || mode == RFmode)
4435 	    return gen_rtx_REG (mode, GR_RET_FIRST);
4444 	  return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
4447       return gen_rtx_REG (mode, GR_RET_FIRST);
4795       /* ??? Check for FP mode.  */
4828 ia64_register_move_cost (enum machine_mode mode, enum reg_class from,
4849   if (mode == XFmode || mode == RFmode)
4852         return MEMORY_MOVE_COST (mode, to, 0);
4865 	return MEMORY_MOVE_COST (mode, to, 0);
4871 	return MEMORY_MOVE_COST (mode, to, 0);
4878 	return MEMORY_MOVE_COST (mode, to, 0);
4937 			     enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
5037      used, e.g., to ensure that kernel mode code doesn't use f32-f127.  */
6671 ia64_mode_to_int (enum machine_mode mode)
6673   switch (mode)
6684       /* ??? This mode needs testing.  Bypasses for ldfp8 instruction are not
6820   /* We should use MEM's mode since REG's mode in presence of ZERO_EXTEND
6842     /* Number of patterns for each speculation mode.  */
6868    speculative pattern for INSN with speculative mode TS, machine mode
9157 		     enum machine_mode mode ATTRIBUTE_UNUSED,
9189 ia64_hpux_function_arg_padding (enum machine_mode mode, tree type)
9198    return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
9369 ia64_select_rtx_section (enum machine_mode mode, rtx x,
9372   if (GET_MODE_SIZE (mode) > 0
9373       && GET_MODE_SIZE (mode) <= ia64_section_threshold
9377     return default_elf_select_rtx_section (mode, x, align);
9582 ia64_scalar_mode_supported_p (enum machine_mode mode)
9584   switch (mode)
9608 ia64_vector_mode_supported_p (enum machine_mode mode)
9610   switch (mode)
9636      We don't need to do that in non canonical PIC mode.  */