config/arm/arm.c

534 /* The register number to be used for the PIC offset register.  */
2583 	 has an offset of zero.  For practical purposes this means
2682   /* On the ARM, the offset starts at 0.  */
3282 	 understands that the PIC register has to be added into the offset.  */
3317       rtx base, offset;
3336       offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3339       if (GET_CODE (offset) == CONST_INT)
3343 	  if (!arm_legitimate_index_p (mode, offset, SET, 0))
3346 	      offset = force_reg (Pmode, offset);
3349 	  if (GET_CODE (offset) == CONST_INT)
3350 	    return plus_constant (base, INTVAL (offset));
3357 	  emit_insn (gen_addsi3 (reg, base, offset));
3361       return gen_rtx_PLUS (Pmode, base, offset);
3799       /* REG+const has 5-7 bit offset for non-SP registers.  */
3806       /* REG+const has 10 bit offset for SP, but only SImode and
3839 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
4140       HOST_WIDE_INT offset = INTVAL (xop1);
4142       /* Try and fold the offset into a biasing of the base register and
4145       if (optimize_size && offset >= 0
4146 	  && offset < 256 + 31 * GET_MODE_SIZE (mode))
4150 	  if (offset >= 256)
4151 	    delta = offset - (256 - GET_MODE_SIZE (mode));
4152 	  else if (offset < 32 * GET_MODE_SIZE (mode) + 8)
4155 	    delta = offset & (~31 * GET_MODE_SIZE (mode));
4157 	  xop0 = force_operand (plus_constant (xop0, offset - delta),
4161       else if (offset < 0 && offset > -256)
5816       /* Don't accept any offset that will require multiple
5823 	 the offset too large.  */
5832 	     to using an ldm instruction unless the offset is zero and
5867       rtx offset;
5880       offset = const0_rtx;
5890 	      && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
5921 	  unsorted_offsets[i] = INTVAL (offset);
5978      if the offset isn't small enough.  The reason 2 ldrs are faster
5988  	ldr	rd1, [rbase + offset]
5989  	ldr	rd2, [rbase + offset + 4]
5993  	add	rd1, rbase, offset
6009   /* Can't do it without setting up the offset, only do this if it takes
6020   HOST_WIDE_INT offset;
6024   switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
6043       if (offset >= 0)
6046 		 (long) offset);
6050 		 (long) -offset);
6094       rtx offset;
6107       offset = const0_rtx;
6117 	      && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
6145 	  unsorted_offsets[i] = INTVAL (offset);
6209   HOST_WIDE_INT offset;
6213   switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
6255   HOST_WIDE_INT offset = *offsetp;
6298 	  mem = adjust_automodify_address (basemem, SImode, addr, offset);
6300 	  offset += 4 * sign;
6306 	  *offsetp = offset;
6328       mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
6331       offset += 4 * sign;
6335     *offsetp = offset;
6344   HOST_WIDE_INT offset = *offsetp;
6361 	  mem = adjust_automodify_address (basemem, SImode, addr, offset);
6363 	  offset += 4 * sign;
6369 	  *offsetp = offset;
6392       mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
6395       offset += 4 * sign;
6399     *offsetp = offset;
6856   HOST_WIDE_INT offset = 0;
6860       offset = SUBREG_BYTE (ref);
6882   /* Handle the case where the address is too complex to be offset by 1.  */
6896       offset += INTVAL (XEXP (base, 1));
6901       lo = (offset >= 0
6902 	    ? (offset & 0xfff)
6903 	    : -((-offset) & 0xfff));
6905       /* Corner case, if lo is the max offset then we would be out of range
6911       hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
6915       gcc_assert (hi + lo == offset);
6925 	  offset = lo;
6940 							       offset))));
6944 							       offset + 1))));
6973   HOST_WIDE_INT offset = 0;
6977       offset = SUBREG_BYTE (ref);
7001   /* Handle the case where the address is too complex to be offset by 1.  */
7041       offset += INTVAL (XEXP (base, 1));
7046       lo = (offset >= 0
7047 	    ? (offset & 0xfff)
7048 	    : -((-offset) & 0xfff));
7050       /* Corner case, if lo is the max offset then we would be out of range
7056       hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
7060       gcc_assert (hi + lo == offset);
7096 	  offset = lo;
7103 					 plus_constant (base, offset + 1)),
7108       emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
7113       emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
7119 					 plus_constant (base, offset + 1)),
7282    able to reach and the offset of the instruction into the function.
7313   /* The maximum offset into the code that this entry can be placed.  While
7323   /* The offset from the start of the minipool.  */
7324   HOST_WIDE_INT offset;
7581   HOST_WIDE_INT offset;
7616   offset = 0;
7619       mp->offset = offset;
7621 	offset += mp->fix_size;
7672 		 + minipool_vector_tail->offset
7695 		   < minipool_barrier->address + mp->offset + fix->fix_size)
7762     mp->offset = 0;
7771 	mp->next->offset = mp->offset + mp->fix_size;
7773 	mp->next->offset = mp->offset;
7784   HOST_WIDE_INT offset = 0;
7791       mp->offset = offset;
7794 	offset += mp->fix_size;
7831 		       (unsigned) mp->offset, (unsigned long) mp->min_address,
8019    minipool.  ADDRESS is the offset of the insn since the start of the
8363 			       this_fix->minipool->offset);
9857   /* Floats_offset is the offset from the "virtual" frame.  In an APCS
9960 	  /* The fldmx insn does not have base+offset addressing modes,
9993 	     old_stack_pointer was double word aligned.  Thus the offset to
10528      into an offset once we have determined the size of preceding data.  */
12060 /* Handle a special case when computing the offset
12067   /* We are only interested if dbxout_parms() failed to compute the offset.  */
12076      an offset of 0 is correct.  */
12081      argument, then an offset of 0 is correct.  */
12088      offset from the frame pointer.  Since GDB only understands
12090      held in the register into an offset from the frame pointer.
12093      register is initialized from the frame pointer plus an offset
12102      an offset of 0 from the frame pointer, rather than 8.  */
13670 /* Like arm_compute_initial_elimination offset.  Simpler because there
14040       unsigned offset;
14081 	  offset = bit_count (l_mask) * UNITS_PER_WORD;
14084 	offset = 0;
14087 		   offset + 16 + current_function_pretend_args_size);
14090 		   offset + 4);
14098 		       offset + 12);
14102 		       offset);
14109 		       offset);
14112 		       offset + 12);
14117 		   offset + 8);
14119 		   offset + 12);
14196   rtx offset;
14237 	base = arg2, offset = arg1;
14239 	base = arg1, offset = arg2;
14244       if (GET_CODE (offset) == REG)
14246 	  int reg_offset = REGNO (offset);
14250 	  /* Add the base and offset registers together into the
14389   HOST_WIDE_INT offset = 0;
14409       offset += 4;
14416 					      plus_constant (in, offset))));
14417       emit_insn (gen_movhi (gen_rtx_MEM (HImode, plus_constant (out, offset)),
14420       offset += 2;
14427 					      plus_constant (in, offset))));
14428       emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (out, offset)),
14633   int offset;
14640   for (offset = 0, chainp = &aof_pic_chain; *chainp;
14641        offset += 4, chainp = &(*chainp)->next)
14643       return plus_constant (aof_pic_label, offset);
14648   return plus_constant (aof_pic_label, offset);
15012   rtx offset;
15019       || GET_CODE (offset = XEXP (sum, 1)) != CONST_INT
15020       || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024)))
15443   HOST_WIDE_INT offset;
15458   offset = -INTVAL (XEXP (XEXP (e, 1), 1));
15466       if (nregs * 4 == offset - 4)
15469 	  offset -= 4;
15476       offset -= 4;
15491   if (offset != nregs * reg_size)
15496   offset = 0;
15527 	  offset += reg_size;
15531 	      || offset != INTVAL (XEXP (e, 1)))
15585 	  HOST_WIDE_INT offset;
15594 	      offset = INTVAL (XEXP (e1, 1));
15618 	  /* Set reg to offset from sp.  */