Lines Matching defs:cycles
1334 2 cycles to load a constant, and the load scheduler may well
1431 never return, and many memory cycles can be saved by not storing
4314 int cycles = 0;
4320 cycles++;
4322 return COSTS_N_INSNS (2) + cycles;
5996 produces worse code -- '3 cycles + any stalls on rd2' instead of
5997 '2 cycles + any stalls on rd2'. On ARMs with only one cache
5999 than 6 cycles, whereas the ldm sequence would only take 5 and
6265 For XScale ldm requires 2 + NREGS cycles to complete and blocks
6274 An ldr instruction takes 1-3 cycles, but does not block the