Lines Matching refs:set
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
46 insn(s) values for the regs they set into the expressions in
70 the condition code for the insn that set the condition code.
86 #include "hard-reg-set.h"
190 last_set_invalid set to nonzero when it is not valid
228 used to store the mode in which the register was last set, the bits
229 that were known to be zero when it was last set, and the number of
230 sign bits copies it was known to have when it was last set. */
237 used. last_set_invalid is set nonzero when this register is being
242 /* Some registers that are set more than once and used in more than one
243 basic block are nevertheless always set in similar ways. For example,
293 get_last_value will not return a value if the register was set at or
342 previously set values, which can be incorrect if a variable is modified
483 set to NEWVAL, do not record this change. Because computing NEWVAL might
759 Also set any known values so that we can use it while searching
760 for what bits are known to be set. */
931 rtx set, note;
933 if ((set = single_set (temp)) != 0
938 && ! unmentioned_reg_p (note, SET_SRC (set))
940 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
941 : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
943 /* Temporarily replace the set's source with the
946 rtx orig = SET_SRC (set);
947 SET_SRC (set) = note;
956 SET_SRC (set) = orig;
1051 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1057 Similarly, set how many bits of X are known to be copies of the sign bit
1059 by any set of X. */
1062 set_nonzero_bits_and_sign_copies (rtx x, rtx set,
1075 if (set == 0 || GET_CODE (set) == CLOBBER)
1084 set = expand_field_assignment (set);
1087 set what we know about X. */
1089 if (SET_DEST (set) == x
1090 || (GET_CODE (SET_DEST (set)) == SUBREG
1091 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1092 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1093 && SUBREG_REG (SET_DEST (set)) == x))
1095 rtx src = SET_SRC (set);
1122 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1142 If the combination is allowed, *PDEST will be set to the single
1151 rtx set = 0, src, dest;
1176 set = PATTERN (insn);
1241 if (set)
1244 set = elt;
1253 if (set == 0
1256 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1262 if (set == 0)
1265 set = expand_field_assignment (set);
1266 src = SET_SRC (set), dest = SET_DEST (set);
1301 If the insns are adjacent, a use can't cross a set even though we
1462 (set (reg:DI 101) (reg:DI 100))
1463 (set (subreg:SI (reg:DI 101) 0) <foo>)
1467 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1468 (set (reg:DI 101) (reg:DI 100))])
1482 into a set of logical operations.
1485 we place a register that is both set and used within I3. If more than one
1498 rtx set = x ;
1499 rtx dest = SET_DEST (set);
1500 rtx src = SET_SRC (set);
1512 i1 or i2 set the same MEM. */
1617 rtx set;
1633 set = single_set (insn);
1634 if (! set)
1636 src = SET_SRC (set);
1637 dest = SET_DEST (set);
1663 likely_spilled_retval_1 (rtx x, rtx set, void *data)
1669 if (!REG_P (XEXP (set, 0)))
1713 /* Disregard parts of the return value that are set later. */
1761 ADDED_SETS is nonzero if the original set is still required. */
1784 /* Check whether X, the destination of a set, refers to part of
1884 code below, set I1 to be the earlier of the two insns. */
1927 (parallel [(set (mem (reg 69)) ...)
1928 (set (reg 69) ...)])
1958 validate the pattern. Everything was set up above. */
2104 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2105 (set Y OP)])
2107 (set Y OP)
2109 (set (reg:CC X) (compare:CC Y (const_int 0)))
2217 instruction: whenever the value set there is still needed past I3.
2218 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2221 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2222 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2223 in I1 needs to be kept around unless I1DEST dies or is set in either
2233 /* If the set in I2 needs to be kept around, we must make a copy of
2258 /* Substitute in the latest insn for the regs set by the earlier ones. */
2266 arithmetic operation and set the condition code. These operations will
2269 The second element of the vector will set some pseudo to the result
2673 /* It is possible that both insns now set the destination of I3.
2700 are set between I2 and I3. */
3163 /* We had one special case above where I2 had more than one set and
3331 rtx i2_insn = 0, i2_val = 0, set;
3333 /* The insn that used to set this register doesn't exist, and
3337 this and I2 set the register to a value that depended on its old
3339 will be set correctly in combine_instructions. */
3342 if ((set = single_set (XEXP (link, 0))) != 0
3343 && rtx_equal_p (i2dest, SET_DEST (set)))
3344 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
3348 /* If the reg formerly set in I2 died only once and that was in I3,
3362 rtx i1_insn = 0, i1_val = 0, set;
3365 if ((set = single_set (XEXP (link, 0))) != 0
3366 && rtx_equal_p (i1dest, SET_DEST (set)))
3367 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
3835 /* Many RISC machines have a large set of logical insns. If the
4000 or PC, so set up to skip this common case. All other cases
4044 /* If this is a register being set, ignore it. */
5199 /* (set (pc) (return)) gets written as (return). */
5281 is a pseudo, we lose unless it is only time we set the pseudo, in
5386 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5388 (set (subreg:m2 x) (op)).
5427 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5451 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5711 bit is not set, as this is easier to optimize. It will be converted
5738 set. */
6138 /* If we know that no extraneous bits are set, and that the high
6139 bit is not set, convert the extraction to the cheaper of
6332 /* If we know that no extraneous bits are set, and that the high
6333 bit is not set, convert extraction to cheaper one - either
6455 address, we stay there. If we have a comparison, set to COMPARE,
6463 /* Process depending on the code of this operation. If NEW is set
6710 *PLEN is set to the length of the field. */
7046 /* If X is (minus C Y) where C's least set bit is larger than any bit
7229 is the number of bits a full-width mask would have set.
7231 hold. If not, we must keep all bits set in nonzero. */
7391 value that is being tested, *PTRUE is set to the value if the rtx being
7392 returned has a nonzero value, and *PFALSE is set to the other alternative.
7394 If we return zero, we set *PTRUE and *PFALSE to X. */
7846 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7860 SRC is an AND with all bits of that field set, then we can discard
8053 above) and set OTHER to the common operand (C in the example).
8178 Note by passing in CONSTOP, we guarantee that the bits not set in
8442 the resulting operation. *PCOMP_P is set to 1 if we would need to
8450 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9006 constant has its sign bit set in shift_mode. */
9275 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9948 a constant that has only a single bit set and are comparing it
9951 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
10343 zero and X is a comparison and C1 and C2 describe only bits set
10896 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10917 /* Set things up so get_last_value is allowed to see anything set up to
10965 /* Now update the status of each register being set.
10966 If someone is using this register in this block, set this register
11014 set is occurring. */
11055 /* Update the records of when each REG was most recently set or killed
11105 the return value register is set at this CUID. We could
11114 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11117 known to have some zero/sign bits set.
11126 rtx links, set;
11136 set = single_set (insn);
11138 if (! set || !REG_P (SET_DEST (set))
11139 || REGNO (SET_DEST (set)) != regno
11140 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11152 if (REG_P (SET_SRC (set)))
11154 regno = REGNO (SET_SRC (set));
11260 mentioned in *LOC are valid when *LOC was part of a value set when
11287 /* If this is a pseudo-register that was only set once and not
11389 it's either a hard register, set more than once, or it's a live
11393 is always set before being used (is never used without being set).
11394 And, if it's set only once, and it's always set before use, then all
11407 /* If the value was set in a later insn than the ones we are processing,
11408 we can't use it even if the register was only set once. */
11430 that is set in an instruction more recent than FROM_CUID. */
11488 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11597 /* CC0 must die in the insn after it is set, so we don't need to take
12007 In that case, we will notice that the register is set in i3,
12014 /* If this register is set or clobbered in I3, put the note there
12185 FROM_INSN for the previous use or set of this register,
12239 /* If the register is being set at TEM, see if that is all
12247 rtx set = single_set (tem);
12253 if (set != 0)
12254 for (inner_dest = SET_DEST (set);
12261 /* Verify that it was the set, and not a clobber that
12269 if (set != 0 && ! side_effects_p (SET_SRC (set))
12272 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12280 First set the pattern to something that won't use
12366 /* If the register is set or already dead at PLACE, we needn't do
12368 We check here if it is set at all, not if is it totally replaced,
12370 set partially. */
12422 not already dead or set. */
12520 rtx set, reg;
12525 set, ignore it. In the latter case, it isn't clear what we
12536 || (set = single_set (XEXP (link, 0))) == 0)
12539 reg = SET_DEST (set);
12547 when we reach a set of the register or the end of the basic block.