binutils/opcodes/cr16-opc.c

29 #define  ARITH_BYTE_INST(NAME, OPC, OP1)                             \
31   {NAME, 1, OPC, 24, ARITH_BYTE_INS, {{uimm4_1,20}, {regr,16}}},     \
33   {NAME, 2, (OPC<<4)+0xB, 20, ARITH_BYTE_INS, {{OP1,0}, {regr,16}}}, \
35   {NAME, 1, OPC+0x1, 24, ARITH_BYTE_INS, {{regr,20}, {regr,16}}}
38 #define  ARITH1_BYTE_INST(NAME, OPC, OP1)                            \
40   {NAME, 2, (OPC<<4)+0xB, 20, ARITH_BYTE_INS, {{OP1,0}, {regr,16}}}
79 #define  ARITH_BYTE_INST1(NAME, OPC)                       \
81   {NAME, 1, OPC, 24, ARITH_BYTE_INS, {{regr,20}, {regr,16}}}
87 #define  ARITH_BYTE_INST2(NAME, OPC)                       \
89   {NAME, 1, OPC, 24, ARITH_BYTE_INS, {{regr,20}, {regp,16}}}
97 #define  ARITH_INST_D(NAME, OPC)                                     \
99   {NAME, 1, OPC, 24, ARITH_INS, {{uimm4_1,20}, {regp,16}}},          \
101   {NAME, 2, (OPC<<4)+0xB, 20, ARITH_INS, {{imm16,0}, {regp,16}}},    \
103   {NAME, 1, OPC+1, 24, ARITH_INS, {{regp,20}, {regp,16}}}
106 #define  ARITH_INST20(NAME, OPC)                        \
108   {NAME, 2, OPC, 24, ARITH_INS, {{uimm20,0},  {regp,20}}}
111 #define  ARITH_INST32(NAME, OPC, OP1)                \
113   {NAME, 3, OPC, 20, ARITH_INS, {{OP1,0},  {regp,16}}}
116 #define  ARITH_INST32RP(NAME, OPC)                   \
118   {NAME, 2, OPC, 12, ARITH_INS, {{regp,4},  {regp,0}}}
138 #define  SHIFT_INST_A(NAME, OPC1, OPC2, SHIFT, OP1, OP2)    \
140   {NAME, 1, OPC1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}},  \
142   {NAME, 1, OPC1+1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}},\
144   {NAME, 1, OPC2, 24, SHIFT_INS, {{regr,20}, {OP2,16}}}
150 #define  SHIFT_INST_L(NAME, OPC1, OPC2, SHIFT, OP1, OP2)    \
152   {NAME, 1, OPC1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}},  \
154   {NAME, 1, OPC2, 24, SHIFT_INS, {{regr,20}, {OP2,16}}}
161 #define  BRANCH_INST(NAME, OPC)                                       \
163   {NAME,  1, OPC, 28, BRANCH_INS, {{cc,20}, {dispe9,16}}},            \
165   {NAME,  2, ((OPC<<4)+0x8), 24, BRANCH_INS, {{cc,20}, {disps17,0}}}, \
167   {NAME,  3, (OPC<<4), 16 , BRANCH_INS, {{cc,4}, {disps25,16}}}
172 #define  BRANCH_NEQ_INST(NAME, OPC)                           \
174   {NAME,  1, OPC, 24, BRANCH_NEQ_INS, {{regr,16}, {disps5,20}}}
183 #define  REG1_INST(NAME, OPC)                  \
185   {NAME,  1, OPC, 20, NO_TYPE_INS, {{regr,16}}}
187 #define  REGP1_INST(NAME, OPC)                \
189   {NAME,  1, OPC, 20, NO_TYPE_INS, {{regp,16}}}
192 #define  REG1_FLAG_INST(NAME, OPC, FLAGS)             \
194   {NAME,  1, OPC, 20, NO_TYPE_INS | FLAGS, {{regp,16}}}
232 #define  REG3_INST(NAME, OPC)                                    \
234   {NAME,  2, OPC,  12, NO_TYPE_INS, {{regr,4}, {regr,0}, {regp,8}}}
242 #define  BR_INST(NAME, OPC)                               \
244   {NAME,  2, OPC,  24, NO_TYPE_INS, {{rra,0}, {disps25,0}}}
246 #define  BR_INST_RP(NAME, OPC)                              \
248   {NAME,  3, OPC,  12, NO_TYPE_INS, {{regp,4}, {disps25,16}}}
253 #define  REGPP2_INST(NAME, OPC)                         \
255   {NAME,  2, OPC,  12, NO_TYPE_INS, {{regp,0}, {regp,4}}}
262 #define  REGLIST_INST(NAME, OPC, TYPE)                               \
264   {NAME,1, (OPC<<1)+1, 23, TYPE, {{uimm3_1,20},{regr,16},{regr,0}}}, \
266   {NAME,  1, OPC, 24, TYPE, {{uimm3_1,20}, {regr,16}}},              \
268   {NAME,  1, (OPC<<8)+0x1E, 16, TYPE, {{regr,0}}}
294 #define  CSTBIT_INST_B(NAME, OP, OPC1, OPC2, OPC3, OPC4)               \
296   {NAME,  2, (OPC3+1), 23, CSTBIT_INS, {{OP,20},{abs20,0}}},           \
298   {NAME,  3, (OPC2+3), 12, CSTBIT_INS, {{OP,4},{abs24,16}}},           \
300   {NAME,  2, OPC1, 24, CSTBIT_INS, {{OP,20}, {rindex7_abs20,0}}},      \
302   {NAME,  2, OPC4, 22, CSTBIT_INS, {{OP,4},{rpindex_disps14,0}}},      \
304   {NAME,  3, OPC2, 12, CSTBIT_INS, {{OP,4}, {rbase_disps20,16}}},      \
306   {NAME,  1, OPC3-2, 23, CSTBIT_INS, {{OP,20}, {rpbase_disps0,16}}},   \
308   {NAME,  2, OPC3,  23, CSTBIT_INS, {{OP,20}, {rpbase_disps16,0}}},    \
310   {NAME,  3, (OPC2+1), 12, CSTBIT_INS, {{OP,4}, {rpbase_disps20,16}}}, \
312   {NAME,  3, (OPC2+2), 12, CSTBIT_INS, {{OP,4}, {rpindex_disps20,16}}}
319 #define  CSTBIT_INST_W(NAME, OP, OPC1, OPC2, OPC3, OPC4)               \
321   {NAME,  2, OPC1+6, 24, CSTBIT_INS, {{OP,20},{abs20,0}}},             \
323   {NAME,  3, OPC2+3, 12, CSTBIT_INS, {{OP,4},{abs24,16}}},             \
325   {NAME,  2, OPC3, 25, CSTBIT_INS, {{OP,20}, {rindex8_abs20,0}}},      \
327   {NAME,  2, OPC4, 22, CSTBIT_INS, {{OP,4},{rpindex_disps14,0}}},      \
329   {NAME,  3, OPC2, 12, CSTBIT_INS, {{OP,4}, {rbase_disps20,16}}},      \
331   {NAME,  1, OPC1+5, 24, CSTBIT_INS, {{OP,20}, {rpbase_disps0,16}}},   \
333   {NAME,  2, OPC1,  24, CSTBIT_INS, {{OP,20}, {rpbase_disps16,0}}},    \
335   {NAME,  3, OPC2+1, 12, CSTBIT_INS, {{OP,4}, {rpbase_disps20,16}}},   \
337   {NAME,  3, OPC2+2, 12, CSTBIT_INS, {{OP,4}, {rpindex_disps20,16}}}
350 #define  LD_REG_INST(NAME, OPC1, OPC2, OPC3, OPC4, OPC5, OP_S, OP_D)     \
352  {NAME, 2, OPC3,  24, LD_STOR_INS, {{abs20,0}, {OP_D,20}}},              \
354  {NAME, 3, OPC1+3, 12, LD_STOR_INS, {{abs24,16}, {OP_D,4}}},             \
356  {NAME, 2, OPC5, 25, LD_STOR_INS, {{rindex8_abs20,0}, {OP_D,20}}},       \
358  {NAME, 1, (OPC2>>4), 28, LD_STOR_INS, {{OP_S,24}, {OP_D,20}}},          \
360  {NAME, 1, OPC2, 24, LD_STOR_INS, {{rpindex_disps0,0}, {OP_D,20}}},      \
362  {NAME, 2, OPC4, 22, LD_STOR_INS, {{rpindex_disps14,0}, {OP_D,20}}},     \
364  {NAME, 3, OPC1+0x60, 12, LD_STOR_INS, {{rbase_dispe20,16}, {OP_D,4}}},  \
366  {NAME, 3, OPC1, 12, LD_STOR_INS, {{rbase_disps20,16}, {OP_D,4}}},       \
368  {NAME, 2, OPC2+1, 24, LD_STOR_INS, {{rpbase_disps16,0}, {OP_D,20}}},    \
370  {NAME, 3, OPC1+1, 12, LD_STOR_INS, {{rpbase_disps20,16}, {OP_D,4}}},    \
372  {NAME, 3, OPC1+0x61, 12, LD_STOR_INS, {{rpbase_dispe20,16}, {OP_D,4}}}, \
374  {NAME, 3, (OPC1+2), 12, LD_STOR_INS, {{rpindex_disps20,16}, {OP_D,4}}}
381 #define  ST_REG_INST(NAME, OPC1, OPC2, OPC3, OPC4, OPC5, OP_D, OP_S)     \
383  {NAME, 2, OPC3,  24, LD_STOR_INS, {{OP_S,20}, {abs20,0}}},              \
385  {NAME, 3, OPC1+3, 12, LD_STOR_INS, {{OP_S,4}, {abs24,16}}},             \
387  {NAME, 2, OPC5, 25, LD_STOR_INS, {{OP_S,20}, {rindex8_abs20,0}}},       \
389  {NAME, 1, (OPC2>>4), 28, LD_STOR_INS, {{OP_S,20}, {OP_D,24}}},          \
391  {NAME, 1, OPC2, 24, LD_STOR_INS, {{OP_S,20}, {rpindex_disps0,0}}},      \
393  {NAME, 2, OPC4, 22, LD_STOR_INS, {{OP_S,20}, {rpindex_disps14,0}}},     \
395  {NAME, 3, OPC1+0x60, 12, LD_STOR_INS, {{OP_S,4}, {rbase_dispe20,16}}},  \
397  {NAME, 3, OPC1, 12, LD_STOR_INS, {{OP_S,4}, {rbase_disps20,16}}},       \
399  {NAME, 2, OPC2+1, 24, LD_STOR_INS, {{OP_S,20}, {rpbase_disps16,0}}},    \
401  {NAME, 3, OPC1+1, 12, LD_STOR_INS, {{OP_S,4}, {rpbase_disps20,16}}},    \
403  {NAME, 3, OPC1+0x61, 12, LD_STOR_INS, {{OP_S,4}, {rpbase_dispe20,16}}}, \
405  {NAME, 3, OPC1+2, 12, LD_STOR_INS, {{OP_S,4}, {rpindex_disps20,16}}}
409 #define  ST_IMM_INST(NAME, OPC1, OPC2, OPC3, OPC4)                       \
411   {NAME,  2, OPC1, 24, LD_STOR_INS, {{uimm4,20},{abs20,0}}},             \
413   {NAME,  3, OPC2+3, 12, LD_STOR_INS, {{uimm4,4},{abs24,16}}},           \
415   {NAME,  2, OPC3, 25, LD_STOR_INS, {{uimm4,20}, {rindex8_abs20,0}}},    \
417   {NAME,  2, OPC4, 22, LD_STOR_INS, {{uimm4,4},{rpindex_disps14,0}}},    \
419   {NAME,  1, OPC1+1, 24, LD_STOR_INS, {{uimm4,20}, {rpbase_disps0,16}}}, \
421   {NAME,  3, OPC2, 12, LD_STOR_INS, {{uimm4,4}, {rbase_disps20,16}}},    \
423   {NAME,  2, OPC1+2, 24, LD_STOR_INS, {{uimm4,20}, {rpbase_disps16,0}}}, \
425   {NAME,  3, OPC2+1, 12, LD_STOR_INS, {{uimm4,4}, {rpbase_disps20,16}}}, \
427   {NAME,  3, OPC2+2, 12, LD_STOR_INS, {{uimm4,4}, {rpindex_disps20,16}}}
436 #define  NO_OP_INST(NAME, OPC)   \
438   {NAME,  1, OPC, 16, 0, {{0, 0}}}
463 #define REG(NAME, N, TYPE)    {STRINGX(NAME), {NAME}, N, TYPE}
465 #define REGP(NAME, BNAME, N, TYPE)    {STRINGX(NAME), {BNAME}, N, TYPE}