nlm/hal/pic.h

59 #define	PIC_IPICTRL_IDB		16 /* interrupt destination base */
68 #define	PIC_IRT_DB		16 /* Destination base */
193 nlm_pic_read_irt(uint64_t base, int irt_index)
195 	return nlm_read_pic_reg(base, PIC_IRT(irt_index));
199 nlm_pic_send_ipi(uint64_t base, int cpu, int vec, int nmi)
211 	nlm_write_pic_reg(base, PIC_IPI_CTL, ipi);
215 nlm_pic_read_control(uint64_t base)
217 	return nlm_read_pic_reg(base, PIC_CTRL);
221 nlm_pic_write_control(uint64_t base, uint64_t control)
223 	nlm_write_pic_reg(base, PIC_CTRL, control);
227 nlm_pic_update_control(uint64_t base, uint64_t control)
231 	val = nlm_read_pic_reg(base, PIC_CTRL);
232 	nlm_write_pic_reg(base, PIC_CTRL, control | val);
236 nlm_pic_ack(uint64_t base, int irt_num)
238 	nlm_write_pic_reg(base, PIC_INT_ACK, irt_num);
242 		nlm_write_pic_reg(base, PIC_STATUS, (1 << irt_num));
246 nlm_set_irt_to_cpu(uint64_t base, int irt, int cpu)
250 	val = nlm_read_pic_reg(base, PIC_IRT(irt));
254 	nlm_write_pic_reg(base, PIC_IRT(irt), val);
258 nlm_pic_write_irt(uint64_t base, int irt_num, int en, int nmi,
268 	nlm_write_pic_reg(base, PIC_IRT(irt_num), val);
272 nlm_pic_write_irt_direct(uint64_t base, int irt_num, int en, int nmi,
275 	nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1,
281 nlm_pic_read_timer(uint64_t base, int timer)
283 	return nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer));
287 nlm_pic_write_timer(uint64_t base, int timer, uint64_t value)
289 	nlm_write_pic_reg(base, PIC_TIMER_COUNT(timer), value);
293 nlm_pic_set_timer(uint64_t base, int timer, uint64_t value, int irq, int cpu)
305 	nlm_write_pic_reg(base, PIC_TIMER_MAXVAL(timer), value);
306 	nlm_pic_write_irt_direct(base, PIC_IRT_TIMER_INDEX(timer),
310 	pic_ctrl = nlm_read_pic_reg(base, PIC_CTRL);
312 	nlm_write_pic_reg(base, PIC_CTRL, pic_ctrl);