Lines Matching refs:port
322 int port, uint32_t cur_flow_base, uint32_t flow_mask,
331 mtu, sc->portcfg[port].vlan_pri_en);
333 port, sc->portcfg[port].free_desc_sizes);
335 port, sc->portcfg[port].ucore_mask);
337 nlm_program_flow_cfg(nae_base, port, cur_flow_base, flow_mask);
340 nlm_configure_sgmii_interface(nae_base, nblock, port, mtu, 0);
342 nlm_config_egress(sc, nblock, context, port, max_channels);
345 nlm_nae_open_if(nae_base, nblock, sc->cmplx_type[nblock], port,
346 sc->portcfg[port].free_desc_sizes);
350 nlm_nae_init_ucore(nae_base, port, ucore_mask);
358 uint32_t cur_flow_base, port, flow_mask;
370 port = 0;
478 int block, int port)
486 p = &(bp->port_ivars[port & 0x3]);
488 sc->portcfg[port].node = p->node;
489 sc->portcfg[port].block = p->block;
490 sc->portcfg[port].port = p->port;
491 sc->portcfg[port].type = p->type;
492 sc->portcfg[port].mdio_bus = p->mdio_bus;
493 sc->portcfg[port].phy_addr = p->phy_addr;
494 sc->portcfg[port].loopback_mode = p->loopback_mode;
495 sc->portcfg[port].num_channels = p->num_channels;
498 block, port, p->free_desc_sizes, MCLBYTES);
501 sc->portcfg[port].free_desc_sizes = p->free_desc_sizes;
504 sc->portcfg[port].ucore_mask = ucore_mask;
505 sc->portcfg[port].vlan_pri_en = p->vlan_pri_en;
506 sc->portcfg[port].num_free_descs = p->num_free_descs;
507 sc->portcfg[port].iface_fifo_size = p->iface_fifo_size;
508 sc->portcfg[port].rxbuf_size = p->rxbuf_size;
509 sc->portcfg[port].rx_slots_reqd = p->rx_slots_reqd;
510 sc->portcfg[port].tx_slots_reqd = p->tx_slots_reqd;
511 sc->portcfg[port].pseq_fifo_size = p->pseq_fifo_size;
513 sc->portcfg[port].stg2_fifo_size = p->stg2_fifo_size;
514 sc->portcfg[port].eh_fifo_size = p->eh_fifo_size;
515 sc->portcfg[port].frout_fifo_size = p->frout_fifo_size;
516 sc->portcfg[port].ms_fifo_size = p->ms_fifo_size;
517 sc->portcfg[port].pkt_fifo_size = p->pkt_fifo_size;
518 sc->portcfg[port].pktlen_fifo_size = p->pktlen_fifo_size;
519 sc->portcfg[port].max_stg2_offset = p->max_stg2_offset;
520 sc->portcfg[port].max_eh_offset = p->max_eh_offset;
521 sc->portcfg[port].max_frout_offset = p->max_frout_offset;
522 sc->portcfg[port].max_ms_offset = p->max_ms_offset;
523 sc->portcfg[port].max_pmem_offset = p->max_pmem_offset;
524 sc->portcfg[port].stg1_2_credit = p->stg1_2_credit;
525 sc->portcfg[port].stg2_eh_credit = p->stg2_eh_credit;
526 sc->portcfg[port].stg2_frout_credit = p->stg2_frout_credit;
527 sc->portcfg[port].stg2_ms_credit = p->stg2_ms_credit;
528 sc->portcfg[port].ieee1588_inc_intg = p->ieee1588_inc_intg;
529 sc->portcfg[port].ieee1588_inc_den = p->ieee1588_inc_den;
530 sc->portcfg[port].ieee1588_inc_num = p->ieee1588_inc_num;
531 sc->portcfg[port].ieee1588_userval = p->ieee1588_userval;
532 sc->portcfg[port].ieee1588_ptpoff = p->ieee1588_ptpoff;
533 sc->portcfg[port].ieee1588_tmr1 = p->ieee1588_tmr1;
534 sc->portcfg[port].ieee1588_tmr2 = p->ieee1588_tmr2;
535 sc->portcfg[port].ieee1588_tmr3 = p->ieee1588_tmr3;
537 sc->total_free_desc += sc->portcfg[port].free_desc_sizes;
548 int port, i, j, nchan, nblock, node, qstart, qnum;
587 cntx2port[i] = 18; /* 18 is an invalid port */
602 port = 0;
610 port += 4;
614 for (j = 0; j < PORTS_PER_CMPLX; j++, port++) {
617 nlm_setup_portcfg(sc, nae_ivars, i, port);
618 nchan = sc->portcfg[port].num_channels;
620 cntx2port[context + offset] = port;
621 sc->portcfg[port].txq = txq_base + context;
622 sc->portcfg[port].rxfreeq = rxvcbase + port;
660 int block, port;
665 port = sc->portcfg[i].port;
668 &(nae_ivars->block_ivars[block].port_ivars[port]));
669 sprintf(desc, "XLP NAE Port %d,%d", block, port);
729 sc->block, sc->port, sc->type, 1 /* broadcast */,
733 sc->block, sc->port, sc->type, 1 /* broadcast */,
738 sc->block, sc->port, sc->type, 1 /* broadcast */,
742 sc->block, sc->port, sc->type, 1 /* broadcast */,
930 nlm_mac_disable(sc->base_addr, sc->block, sc->type, sc->port);
956 nlm_mac_enable(sc->base_addr, sc->block, sc->type, sc->port);
995 /* last octet is port specific */
996 sc->dev_addr[5] += (sc->block * 4) + sc->port;
1000 sc->port, sc->type, sc->dev_addr);
1003 sc->port, sc->type, sc->dev_addr);
1041 int port = sc->block * 4 + sc->port;
1045 /*(sc->network_sc)->ifp_ports[port].xlpge_if = ifp;*/
1046 ifp_ports[port].xlpge_if = ifp;
1145 reg = SGMII_STATS_MLR(sc->block, sc->port) + field;
1216 int port;
1224 sc->port = pv->port;
1247 port = (sc->block*4)+sc->port;
1248 sc->nfree_desc = nae_port_config[port].num_free_descs;
1249 sc->txq = nae_port_config[port].txq;
1250 sc->rxfreeq = nae_port_config[port].rxfreeq;
1255 sc->block, sc->port);
1258 ifp_ports[port].xlpge_sc = sc;
1355 sc->block, sc->port, speed, duplexity);
1357 nlm_nae_setup_mac(sc->base_addr, sc->block, sc->port, 0, 1, 1,
1387 nlm_xlpge_rx(struct nlm_xlpge_softc *sc, int port, vm_paddr_t paddr, int len)
1438 if (port == 16 || port == 17)
1492 uint32_t port = 0;
1505 port = cntx2port[context];
1507 if (port >= XLP_MAX_PORTS) {
1508 printf("%s:%d Bad port %d (context=%d)\n",
1509 __func__, __LINE__, port, context);
1512 ifp = ifp_ports[port].xlpge_if;
1513 xlpge_sc = ifp_ports[port].xlpge_sc;
1529 port = cntx2port[context];
1531 if (port >= XLP_MAX_PORTS) {
1532 printf("%s:%d Bad port %d (context=%d)\n",
1533 __func__, __LINE__, port, context);
1537 ifp = ifp_ports[port].xlpge_if;
1538 xlpge_sc = ifp_ports[port].xlpge_sc;
1540 nlm_xlpge_rx(xlpge_sc, port, phys_addr, length);