dev/net/nae.c

82 	int rx_slots = 0, port;
86 	for (port = 0; port < total_num_ports; port++) {
87 		if (cfg[port].rx_slots_reqd)
88 		    rx_slots += cfg[port].rx_slots_reqd;
101 		for (port = 0; port < total_num_ports; port++) {
102 			if (cfg[port].rx_slots_reqd > 0) {
103 				val = (cal_len << 16) | (port << 8) | cal;
107 				cfg[port].rx_slots_reqd--;
119 	int tx_slots = 0, port;
123 	for (port = 0; port < total_num_ports; port++) {
124 		if (cfg[port].tx_slots_reqd)
125 			tx_slots += cfg[port].tx_slots_reqd;
137 		for (port = 0; port < total_num_ports; port++) {
138 			if (cfg[port].tx_slots_reqd > 0) {
139 				val = (port << 7) | (cal << 1) | 1;
143 				cfg[port].tx_slots_reqd--;
358 nlm_program_flow_cfg(uint64_t nae_base, int port,
363 	val = (cur_flow_base << 16) | port;
750 nlm_config_freein_fifo_uniq_cfg(uint64_t nae_base, int port,
757 	val = (size_in_clines << 8) | (port & 0x1f);
763 nlm_config_ucore_iface_mask_cfg(uint64_t nae_base, int port,
769 	    (port & 0x1f);
937     uint32_t l3cm, uint32_t l4pm, uint32_t port,
945 	    ((port & 0x1f) << 12)	|
1191 nlm_enable_hardware_parser_per_port(uint64_t nae_base, int block, int port)
1193 	int hwport = (block * 4) + (port & 0x3);
1195 	/* program L2 and L3 header extraction for each port */
1196 	/* enable ethernet L2 mode on port */
1261 nlm_mac_enable(uint64_t nae_base, int nblock, int port_type, int port)
1265 	int iface = port & 0x3;
1298 nlm_mac_disable(uint64_t nae_base, int nblock, int port_type, int port)
1302 	int iface = port & 0x3;
1357     int port, uint32_t desc_size)
1371 		nlm_nae_set_ior_credit(nae_base, 0xf << port, 0xf << port);
1375 		nlm_nae_set_ior_credit(nae_base, 0xff << port, 0xff << port);
1379 		nlm_nae_set_ior_credit(nae_base, 0x1 << port, 0);
1386 		iface = port & 0x3;
1393 		netwk_inf |= (port << 27);
1396 		/* Sofreset sgmii port - set bit 11 to 0  */