vxge/vxgehal/vxgehal-virtualpath.c

45  * @data1: Buffer to return data 1 register contents
59     u64 *data1)
64 	vxge_assert((vpath_reg != NULL) && (data0 != NULL) && (data1 != NULL));
73 	    "data1 = 0x"VXGE_OS_STXFMT, (ptr_t) pdev, (ptr_t) regh0,
75 	    (ptr_t) data0, (ptr_t) data1);
136 		*data1 = vxge_os_pio_mem_read64(pdev, regh0,
178 	u64 data1 = 0ULL;
203 	    &data1, &data2);
213 	    (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FW_VER_DAY(data1);
215 	    (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MONTH(data1);
217 	    (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FW_VER_YEAR(data1);
224 	    (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(data1);
226 	    (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(data1);
228 	    (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(data1);
238 	    &data1, &data2);
248 	    (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FLASH_VER_DAY(data1);
250 	    (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FLASH_VER_MONTH(data1);
252 	    (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FLASH_VER_YEAR(data1);
259 	    (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FLASH_VER_MAJOR(data1);
261 	    (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FLASH_VER_MINOR(data1);
263 	    (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FLASH_VER_BUILD(data1);
301 	u64 data1 = 0ULL;
328 	    &data1, &data2);
338 	((u64 *) serial_number)[0] = vxge_os_ntohll(data1);
346 	    &data1, &data2);
356 	((u64 *) part_number)[0] = vxge_os_ntohll(data1);
370 		    &data1, &data2);
380 		((u64 *) product_description)[j++] = vxge_os_ntohll(data1);
417 	u64 data1 = 0ULL;
439 	    &data1, &data2);
448 	*ports = (u32) data1;
453 	    &data1, &data2);
462 	if (data1) {
464 		pmd_port0->type = (u32) data1;
469 		    &data1, &data2);
479 		((u64 *) pmd_port0->vendor)[0] = vxge_os_ntohll(data1);
487 		    &data1, &data2);
497 		((u64 *) pmd_port0->part_num)[0] = vxge_os_ntohll(data1);
505 		    &data1, &data2);
515 		((u64 *) pmd_port0->ser_num)[0] = vxge_os_ntohll(data1);
526 	    &data1, &data2);
535 	if (data1) {
537 		pmd_port1->type = (u32) data1;
542 		    &data1, &data2);
552 		((u64 *) pmd_port1->vendor)[0] = vxge_os_ntohll(data1);
560 		    &data1, &data2);
570 		((u64 *) pmd_port1->part_num)[0] = vxge_os_ntohll(data1);
578 		    &data1, &data2);
588 		((u64 *) pmd_port1->ser_num)[0] = vxge_os_ntohll(data1);
621 	u64 data1 = 0ULL;
638 	    &data1, &data2);
643 	return (data1);
655 	u64 data1 = 0ULL;
675 	    &data1, &data2);
677 	if (VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_MEMO_ITEM_STATUS(data1) ==
712 	u64 data1 = 0ULL;
730 	    &data1, &data2);
1454  * @data1: Pointer to the data 1 to be read from the table
1466     u64 *data1,
1475 	    (data1 != NULL) && (data2 != NULL));
1486 	    "offset = %d, data1 = 0x"VXGE_OS_STXFMT", data2 = 0x"VXGE_OS_STXFMT,
1487 	    (ptr_t) vpath_handle, action, rts_table, offset, (ptr_t) data1,
1547 	*data1 = vxge_os_pio_mem_read64(
1603  * @data1: data 1 to be written to the table
1615     u64 data1,
1634 	    "offset = %d, data1 = 0x"VXGE_OS_LLXFMT", data2 = 0x"VXGE_OS_LLXFMT,
1635 	    (ptr_t) vpath_handle, action, rts_table, offset, data1, data2);
1639 	    data1,
1731 	u64 data1 = 0ULL;
1755 		data1 <<= 8;
1756 		data1 |= (u8) macaddr[i];
1786 	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_DA_MAC_ADDR(data1),
1824 	u64 data1 = 0ULL;
1881 			data1 = vxge_os_pio_mem_read64(pdev, regh0,
1885 			data1 =
1886 			    VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(data1);
1890 			if (VXGE_HAL_IS_UNICAST(data1)) {
1893 					macaddr[i - 1] = (u8) (data1 & 0xFF);
1894 					data1 >>= 8;
1935 	u64 data1 = 0ULL;
1955 	    &data1,
1965 	data1 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(data1);
1970 		macaddr[i - 1] = (u8) (data1 & 0xFF);
1971 		data1 >>= 8;
2005 	u64 data1 = 0ULL;
2025 	    &data1,
2035 	data1 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(data1);
2040 		macaddr[i - 1] = (u8) (data1 & 0xFF);
2041 		data1 >>= 8;
2075 	u64 data1 = 0ULL;
2097 		data1 <<= 8;
2098 		data1 |= (u8) macaddr[i];
2110 	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_DA_MAC_ADDR(data1),
2724 	u64 data0, data1;
2749 	    &data1);
3312 	u64 data1;
3333 			data1 = 0;
3343 			    data1);
3357 			data1 = 0;
3365 			    j, data0, data1);
3401 					data1 =
3419 					    data1);
3462 	u64 data1;
3490 				    &data1);
3513 				data1 = 0;
3523 					data1 = VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_NUM(j + 2);
3526 					data1 |= VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_NUM(j + 3);
3532 				    0, &data0, &data1);
3562 					    VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM0_ENTRY_EN(data1)) {
3570 					    VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM1_ENTRY_EN(data1)) {
3599 	u64 data0, data1;
3623 			data1 = 0;
3630 			    data1);
3650 				data1 =
3659 				    data1);
11398     u64 data0, u64 data1)
11417 	    hldev->header.regh0, data1,
11466 	u64 data0 = 0x0, data1 = 0x0;
11482 	status = vxge_hal_set_fw_api(devh, 0, action, 0x0, data0, data1);
11503 	u64 data0 = 0x0, data1 = 0x0;
11516 	data1 = port_mode;
11519 	status = vxge_hal_set_fw_api(devh, 0, action, 0x0, data0, data1);
11534 	u64 data0 = 0x0, data1 = 0x0;
11548 	data1 = behave_on_failure;
11551 	status = vxge_hal_set_fw_api(devh, 0, action, 0x0, data0, data1);
11561 	u64 data0 = 0x0, data1 = 0x0;
11575 	data1 = l2_switch;
11578 	status = vxge_hal_set_fw_api(devh, 0, action, 0x0, data0, data1);
11651 	u64 data0 = 0x0, data1 = 0x0;
11657 	data1 = port_map;
11659 	status = vxge_hal_set_fw_api(devh, 0, action, 0x0, data0, data1);
11666     u32 vf_id, u32 * num_vp, u64 * data1)
11689 		*data1 = vxge_os_pio_mem_read64(hldev->header.pdev,
11725 	u64 data0 = 0x0, data1 = 0x0;
11748 	status = vxge_hal_set_fw_api(devh, 0, action, 0x0, data0, data1);
11752 	data1 = vxge_os_pio_mem_read64(hldev->header.pdev,
11763 		data1 &= ~VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_RX_MAX_BW(0xff);
11765 		data1 |=
11767 		data1 |= VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_VPATH_OR_FUNC(1);
11773 		data1 &= ~VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_RX_PRIORITY(0x7);
11774 		data1 |=
11780 		    0x0, data0, data1);
11789 	u64 data0 = 0x0, data1 = 0x0;
11812 	status = vxge_hal_set_fw_api(devh, 0, action, 0x0, data0, data1);
11816 	data1 = vxge_os_pio_mem_read64(hldev->header.pdev,
11827 		data1 &= ~VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_TX_MAX_BW(0xff);
11829 		data1 |=
11836 		data1 &= ~VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_TX_PRIORITY(0x7);
11837 		data1 |=
11843 		    0x0, data0, data1);
11854 	u64 data0 = 0x0, data1 = 0x0;
11867 	status = vxge_hal_set_fw_api(devh, 0, action, 0x0, data0, data1);
11871 	data1 = vxge_os_pio_mem_read64(hldev->header.pdev,
11875 	*priority = (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RX_PRIORITY(data1);
11881 	*bandwidth = (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RX_MAX_BW(data1);
11892 	u64 data0 = 0x0, data1 = 0x0;
11905 	status = vxge_hal_set_fw_api(devh, func_id, action, 0x0, data0, data1);
11909 	data1 = vxge_os_pio_mem_read64(hldev->header.pdev,
11914 	    (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RX_PRIORITY(data1);
11920 	*bandwidth = (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RX_MAX_BW(data1);
12113 	u64 data0 = 0x0, data1 = 0x0;
12126 		    data0, data1);