Lines Matching refs:vxge_hal_device_h
97 vxge_hal_mgmt_about(vxge_hal_device_h devh,
119 vxge_hal_mgmt_pci_config(vxge_hal_device_h devh, u8 *buffer, u32 *size);
179 vxge_hal_mgmt_pm_capabilities_get(vxge_hal_device_h devh,
204 vxge_hal_mgmt_sid_capabilities_get(vxge_hal_device_h devh,
263 vxge_hal_mgmt_msi_capabilities_get(vxge_hal_device_h devh,
274 vxge_hal_mgmt_msi_capabilities_set(vxge_hal_device_h devh,
313 vxge_hal_mgmt_msix_capabilities_get(vxge_hal_device_h devh,
400 vxge_hal_mgmt_pci_err_capabilities_get(vxge_hal_device_h devh,
466 vxge_hal_mgmt_device_config(vxge_hal_device_h devh,
489 vxge_hal_mgmt_pcireg_read(vxge_hal_device_h devh, unsigned int offset,
538 vxge_hal_mgmt_reg_read(vxge_hal_device_h devh,
563 vxge_hal_mgmt_reg_write(vxge_hal_device_h devh,
583 vxge_hal_mgmt_bar0_read(vxge_hal_device_h devh,
601 vxge_hal_mgmt_bar1_read(vxge_hal_device_h devh,
619 vxge_hal_mgmt_bar0_write(vxge_hal_device_h devh,
644 vxge_hal_mgmt_register_config(vxge_hal_device_h devh,
658 u32 vxge_hal_mgmt_read_xfp_current_temp(vxge_hal_device_h devh, u32 port);
671 vxge_hal_mgmt_pma_loopback(vxge_hal_device_h devh, u32 port, u32 enable);
684 vxge_hal_mgmt_xgmii_loopback(vxge_hal_device_h devh, u32 port, u32 enable);