sallsdk/spc/sahw.c

325           ret = siSpcSoftReset(agRoot, SPC_SOFT_RESET_SIGNATURE);
463         siSpcSoftReset(agRoot, SPC_HDASOFT_RESET_SIGNATURE);
477         siSpcSoftReset(agRoot, SPC_SOFT_RESET_SIGNATURE);
504        siSpcSoftReset(agRoot, SPC_SOFT_RESET_SIGNATURE);
885     ret = siSpcSoftReset(agRoot, signature  );
917  *  The siSpcSoftReset() function is called to soft reset SPC. Upon return,
926 GLOBAL bit32 siSpcSoftReset(
945     SA_DBG1(("siSpcSoftReset: start\n"));
951     SA_DBG1(("siSpcSoftReset: ResetCount = 0x%x\n", gLLSoftResetCounter));
957     /* TP:Q1 siSpcSoftReset */
972     /* TP:Q2 siSpcSoftReset */
975       SA_DBG1(("siSpcSoftReset:Shift Bar4 to 0x%x failed\n", MBIC_AAP1_ADDR_BASE));
981       SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",1));
986     ossaHwRegWriteExt(agRoot, PCIBAR2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0);   /* siSpcSoftReset */
991       SA_DBG1(("siSpcSoftReset:Shift Bar4 to 0x%x failed\n", MBIC_IOP_ADDR_BASE));
996       SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",2));
1001     ossaHwRegWriteExt(agRoot, PCIBAR2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0); /* siSpcSoftReset */
1005     ossaHwRegWriteExt(agRoot, PCIBAR1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0); /* siSpcSoftReset */
1009     ossaHwRegWriteExt(agRoot, PCIBAR1, PCIE_EVENT_INTERRUPT, regVal);  /* siSpcSoftReset */
1013     ossaHwRegWriteExt(agRoot, PCIBAR1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0); /* siSpcSoftReset */
1017     ossaHwRegWriteExt(agRoot, PCIBAR1, PCIE_ERROR_INTERRUPT, regVal); /* siSpcSoftReset */
1030       SA_DBG1(("siSpcSoftReset:Shift Bar4 to 0x%x failed\n", GSM_ADDR_BASE));
1035       SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",3));
1042     /* TP:Q3 siSpcSoftReset */
1056     ossaHwRegWriteExt(agRoot, PCIBAR2, GSM_CONFIG_RESET, regVal); /* siSpcSoftReset */
1071     /* TP:Q4 siSpcSoftReset */
1074     ossaHwRegWriteExt(agRoot, PCIBAR2, GSM_READ_ADDR_PARITY_CHECK, 0x0); /* siSpcSoftReset */
1080     ossaHwRegWriteExt(agRoot, PCIBAR2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0); /* siSpcSoftReset */
1086     ossaHwRegWriteExt(agRoot, PCIBAR2, GSM_WRITE_DATA_PARITY_CHECK, 0x0); /* siSpcSoftReset */
1090     /* TP:Q5 siSpcSoftReset */
1096       SA_DBG1(("siSpcSoftReset:Shift Bar4 to 0x%x failed\n", GPIO_ADDR_BASE));
1101       SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",4));
1108     ossaHwRegWriteExt(agRoot, PCIBAR2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal); /* siSpcSoftReset */
1113     /* TP:Q6 siSpcSoftReset */
1116       SA_DBG1(("siSpcSoftReset:Shift Bar4 to 0x%x failed\n", SPC_TOP_LEVEL_ADDR_BASE));
1121       SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",5));
1127     ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_RESET, regVal); /* siSpcSoftReset */
1131     /* TP:Q7 siSpcSoftReset */
1135     ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_RESET, regVal); /* siSpcSoftReset */
1139     /* TP:Q8 siSpcSoftReset */
1145     /* TP:Q9 siSpcSoftReset */
1149     ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_RESET, regVal); /* siSpcSoftReset */
1153     /* TP:QA siSpcSoftReset */
1159     /* TP:QB siSpcSoftReset */
1162       SA_DBG1(("siSpcSoftReset:Shift Bar4 to 0x%x failed\n", GSM_ADDR_BASE));
1167       SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",5));
1181     ossaHwRegWriteExt(agRoot, PCIBAR2, GSM_CONFIG_RESET, regVal); /* siSpcSoftReset */
1194     /* TP:QC siSpcSoftReset */
1197     ossaHwRegWriteExt(agRoot, PCIBAR2, GSM_READ_ADDR_PARITY_CHECK, regVal1); /* siSpcSoftReset */
1203     ossaHwRegWriteExt(agRoot, PCIBAR2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2); /* siSpcSoftReset */
1209     ossaHwRegWriteExt(agRoot, PCIBAR2, GSM_WRITE_DATA_PARITY_CHECK, regVal3); /* siSpcSoftReset */
1215     /* TP:QD siSpcSoftReset */
1218       SA_DBG1(("siSpcSoftReset:Shift Bar4 to 0x%x failed\n", SPC_TOP_LEVEL_ADDR_BASE));
1223       SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",7));
1229     ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_RESET, regVal); /* siSpcSoftReset */
1256             SA_DBG1(("siSpcSoftReset: TIMEOUT:ToggleVal 0x%x, MSGU_SCRATCH_PAD1 = 0x%x\n", toggleVal, regVal));
1262             SA_DBG1(("siSpcSoftReset: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0)));
1263             SA_DBG1(("siSpcSoftReset: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2)));
1264             SA_DBG1(("siSpcSoftReset: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3)));
1266             SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",8));
1272         /* TP:QG siSpcSoftReset */
1281         SA_DBG1(("siSpcSoftReset: HDA Soft Reset Complete\n"));
1294        SA_DBG1(("siSpcSoftReset: SPC FW not ready SCRATCH_PAD1 = 0x%x\n", regVal));
1297        SA_DBG1(("siSpcSoftReset: SPC FW not ready SCRATCH_PAD2 = 0x%x\n", regVal));
1303        SA_DBG1(("siSpcSoftReset: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0)));
1304        SA_DBG1(("siSpcSoftReset: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3)));
1306        SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",9));
1310     /* TP:QI siSpcSoftReset */
1317     SA_DBG1(("siSpcSoftReset: Soft Reset Complete\n"));
1503       siSpcSoftReset(agRoot, SPC_HDASOFT_RESET_SIGNATURE);
1537         siSpcSoftReset(agRoot, SPC_HDASOFT_RESET_SIGNATURE);
1658         siSpcSoftReset(agRoot, SPC_HDASOFT_RESET_SIGNATURE);
2674         SA_DBG1(("siSpcSoftReset:Shift Bar4 to 0x%x failed\n", RB6_ACCESS_REG));