dev/e1000/e1000_ich8lan.c

202 	u16 phy_reg = 0;
209 		ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
210 		if (ret_val || (phy_reg == 0xFFFF))
212 		phy_id = (u32)(phy_reg << 16);
214 		ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
215 		if (ret_val || (phy_reg == 0xFFFF)) {
219 		phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
228 		hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
252 			hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
253 			phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
254 			hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);
1263 	u16 phy_reg;
1309 	ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1312 	phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1313 	e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1329 		phy_reg = oem_reg;
1330 		phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
1333 							phy_reg);
1342 	ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1345 	phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1349 			phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1351 			phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1353 		phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1354 		phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1356 		phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1357 		phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1358 		phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1360 	e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1368 	phy_reg |= I218_ULP_CONFIG1_START;
1369 	e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1409 	u16 phy_reg;
1464 	ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1476 						       &phy_reg);
1480 	phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1481 	e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1491 	ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1494 	phy_reg |= HV_PM_CTRL_K1_ENABLE;
1495 	e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1498 	ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1501 		phy_reg &= ~(I218_ULP_CONFIG1_IND |
1509 		e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1512 		phy_reg |= I218_ULP_CONFIG1_START;
1513 		e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1549 	u16 phy_reg;
1616 			u16 phy_reg;
1619 						    &phy_reg);
1620 			phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1622 				phy_reg |= 0x3E8;
1624 				phy_reg |= 0xFA;
1627 						     phy_reg);
1752 		hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1753 		phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1757 			phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1759 		hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
2150 	u16 phy_reg = 0;
2162 	ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2175 	e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2695 	u16 i, phy_reg = 0;
2703 	ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2723 	e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2756 	u16 phy_reg, data;
2766 	hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
2768 					phy_reg | (1 << 14));
2918 	return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
5631 		u16 phy_reg, device_id = hw->device_id;
5673 							    &phy_reg);
5674 				phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5677 							     phy_reg);
5692 						    &phy_reg);
5693 			phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
5695 						     phy_reg);
5700 			hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg);
5701 			phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
5702 			hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg);
5705 			hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg);
5706 			phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
5707 			hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5713 		hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg);
5714 		phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
5715 		hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5773 		u16 phy_reg;
5782 		hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5783 		phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5784 		hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5792 							      &phy_reg);
5795 			phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5796 			hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5803 						      &phy_reg);
5806 		phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5807 		hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);