drm2/i915/intel_ringbuffer.c

93 	intel_ring_emit(ring, cmd);
94 	intel_ring_emit(ring, MI_NOOP);
151 	intel_ring_emit(ring, cmd);
152 	intel_ring_emit(ring, MI_NOOP);
207 	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
208 	intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
210 	intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
211 	intel_ring_emit(ring, 0); /* low dword */
212 	intel_ring_emit(ring, 0); /* high dword */
213 	intel_ring_emit(ring, MI_NOOP);
220 	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
221 	intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
222 	intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
223 	intel_ring_emit(ring, 0);
224 	intel_ring_emit(ring, 0);
225 	intel_ring_emit(ring, MI_NOOP);
259 	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
260 	intel_ring_emit(ring, flags);
261 	intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
262 	intel_ring_emit(ring, 0); /* lower dword */
263 	intel_ring_emit(ring, 0); /* uppwer dword */
264 	intel_ring_emit(ring, MI_NOOP);
479 	intel_ring_emit(ring, MI_SEMAPHORE_MBOX |
483 	intel_ring_emit(ring, seqno);
484 	intel_ring_emit(ring, mmio_offset);
515 	intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
516 	intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
517 	intel_ring_emit(ring, *seqno);
518 	intel_ring_emit(ring, MI_USER_INTERRUPT);
556 	intel_ring_emit(waiter,
558 	intel_ring_emit(waiter, seqno);
559 	intel_ring_emit(waiter, 0);
560 	intel_ring_emit(waiter, MI_NOOP);
575 	intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |		\
577 	intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);			\
578 	intel_ring_emit(ring__, 0);							\
579 	intel_ring_emit(ring__, 0);							\
603 	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
606 	intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
607 	intel_ring_emit(ring, seqno);
608 	intel_ring_emit(ring, 0);
620 	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
624 	intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
625 	intel_ring_emit(ring, seqno);
626 	intel_ring_emit(ring, 0);
805 	intel_ring_emit(ring, MI_FLUSH);
806 	intel_ring_emit(ring, MI_NOOP);
824 	intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
825 	intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
826 	intel_ring_emit(ring, seqno);
827 	intel_ring_emit(ring, MI_USER_INTERRUPT);
882 	intel_ring_emit(ring,
886 	intel_ring_emit(ring, offset);
902 	intel_ring_emit(ring, MI_BATCH_BUFFER);
903 	intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
904 	intel_ring_emit(ring, offset + len - 8);
905 	intel_ring_emit(ring, 0);
921 	intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
922 	intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
1298 	intel_ring_emit(ring, cmd);
1299 	intel_ring_emit(ring, 0);
1300 	intel_ring_emit(ring, 0);
1301 	intel_ring_emit(ring, MI_NOOP);
1316 	intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
1318 	intel_ring_emit(ring, offset);
1339 	intel_ring_emit(ring, cmd);
1340 	intel_ring_emit(ring, 0);
1341 	intel_ring_emit(ring, 0);
1342 	intel_ring_emit(ring, MI_NOOP);