drm2/i915/intel_ddi.c

67 /* On Haswell, DDI port buffers must be programmed with correct values
73 static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port, bool use_fdi_mode)
82 	DRM_DEBUG_DRIVER("Initializing DDI buffers for port %c in %s mode\n",
83 			port_name(port),
86 	if (use_fdi_mode && (port != PORT_E))
87 		DRM_DEBUG_KMS("Programming port %c in FDI mode, this probably will not work.\n",
88 		port_name(port));
90 	for (i=0, reg=DDI_BUF_TRANS(port); i < DRM_ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
97  * mode and port E for FDI.
101 	int port;
104 		for (port = PORT_A; port < PORT_E; port++)
105 			intel_prepare_ddi_buffers(dev, port, false);
130  * both the DDI port and PCH receiver for the desired DDI buffer settings.
132  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
231  * same DDI port, such as HDMI or DP or even VGA via FDI. So we don't know by
236 void intel_ddi_init(struct drm_device *dev, enum port port)
241 	switch(port){
244 		DRM_DEBUG_DRIVER("Found digital output on DDI port A\n");
250 		intel_hdmi_init(dev, DDI_BUF_CTL(port));
253 		DRM_DEBUG_DRIVER("No handlers defined for port %d, skipping DDI initialization\n",
254 				port);
656 	int port = intel_hdmi->ddi_port;
664 	DRM_DEBUG_KMS("Preparing HDMI DDI mode for Haswell on port %c, pipe %c\n", port_name(port), pipe_name(pipe));
704 	/* Use WRPLL1 clock to drive the output to the port, and tell the pipe to use
705 	 * this port for connection.
707 	I915_WRITE(PORT_CLK_SEL(port),
710 			PIPE_CLK_SEL_PORT(port));
726 	temp |= PIPE_DDI_SELECT_PORT(port) |
744 	int port = intel_hdmi->ddi_port;
747 	temp = I915_READ(DDI_BUF_CTL(port));
755 	/* Enable DDI_BUF_CTL. In HDMI/DVI mode, the port width,
757 	 * to be done besides enabling the port.
759 	I915_WRITE(DDI_BUF_CTL(port),