dev/cxgb/cxgb_sge.c

1132 txq_prod(struct sge_txq *txq, unsigned int ndesc, struct txq_state *txqs)
1139 	txqs->gen = txq->gen;
1141 	txqs->compl = (txq->unacked & 32) << (S_WR_COMPL - 5);
1143 	txqs->pidx = txq->pidx;
1146 	if (((txqs->pidx > txq->cidx) &&
1147 		(txq->pidx < txqs->pidx) &&
1149 	    ((txqs->pidx < txq->cidx) &&
1151 	    ((txqs->pidx < txq->cidx) &&
1152 		(txq->cidx < txqs->pidx)))
1153 		panic("txqs->pidx=%d txq->pidx=%d txq->cidx=%d",
1154 		    txqs->pidx, txq->pidx, txq->cidx);
1269  *	@txqs: txq state (generation and producer index)
1283 write_wr_hdr_sgl(unsigned int ndesc, struct tx_desc *txd, struct txq_state *txqs,
1289 	struct tx_sw_desc *txsd = &txq->sdesc[txqs->pidx];
1294 		    htonl(V_WR_LEN(flits + sgl_flits) | V_WR_GEN(txqs->gen)) |
1297 		wr_gen2(txd, txqs->gen);
1300 		unsigned int ogen = txqs->gen;
1321 			if (++txqs->pidx == txq->size) {
1322 				txqs->pidx = 0;
1323 				txqs->gen ^= 1;
1338 			    V_WR_GEN(txqs->gen)) | wr_lo;
1339 			wr_gen2(txd, txqs->gen);
1364 	struct txq_state txqs;
1409 	txq_prod(txq, ndesc, &txqs);
1450 		    htonl(V_WR_OP(FW_WROPCODE_TUNNEL_TX_PKT) | txqs.compl);
1452 		    V_WR_GEN(txqs.gen)) | htonl(V_WR_TID(txq->token));
1456 		wr_gen2(txd, txqs.gen);
1532 					  F_WR_SOP | F_WR_EOP | txqs.compl);
1534 			    V_WR_GEN(txqs.gen) | V_WR_TID(txq->token));
1538 			wr_gen2(txd, txqs.gen);
1564 					  F_WR_SOP | F_WR_EOP | txqs.compl);
1566 			    V_WR_GEN(txqs.gen) | V_WR_TID(txq->token));
1570 			wr_gen2(txd, txqs.gen);
1586 	wr_hi = htonl(V_WR_OP(FW_WROPCODE_TUNNEL_TX_PKT) | txqs.compl);
1588 	write_wr_hdr_sgl(ndesc, txd, &txqs, txq, sgl, flits,
2212 	struct txq_state txqs;
2255 	txqs.gen = gen;
2256 	txqs.pidx = pidx;
2257 	txqs.compl = 0;
2259 	write_wr_hdr_sgl(ndesc, d, &txqs, q, t3sgl, flits, sgl_flits,