Lines Matching refs:CAS_WRITE_4
330 CAS_WRITE_4(sc, CAS_PCS_DATAPATH, CAS_PCS_DATAPATH_MII);
341 CAS_WRITE_4(sc, CAS_MIF_CONF, v);
346 CAS_WRITE_4(sc, CAS_SATURN_PCFG,
363 CAS_WRITE_4(sc, CAS_MIF_CONF, v);
368 CAS_WRITE_4(sc, CAS_SATURN_PCFG,
384 CAS_WRITE_4(sc, CAS_PCS_DATAPATH, CAS_PCS_DATAPATH_SERDES);
388 CAS_WRITE_4(sc, CAS_SATURN_PCFG, 0);
392 CAS_WRITE_4(sc, CAS_PCS_SERDES_CTRL, CAS_PCS_SERDES_CTRL_ESD);
395 CAS_WRITE_4(sc, CAS_PCS_CONF, CAS_PCS_CONF_EN);
660 CAS_WRITE_4(sc, CAS_MAC_NORM_COLL_CNT, 0);
661 CAS_WRITE_4(sc, CAS_MAC_FIRST_COLL_CNT, 0);
662 CAS_WRITE_4(sc, CAS_MAC_EXCESS_COLL_CNT, 0);
663 CAS_WRITE_4(sc, CAS_MAC_LATE_COLL_CNT, 0);
664 CAS_WRITE_4(sc, CAS_MAC_RX_LEN_ERR_CNT, 0);
665 CAS_WRITE_4(sc, CAS_MAC_RX_ALIGN_ERR, 0);
666 CAS_WRITE_4(sc, CAS_MAC_RX_CRC_ERR_CNT, 0);
667 CAS_WRITE_4(sc, CAS_MAC_RX_CODE_VIOL, 0);
701 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff);
710 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX |
733 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff);
772 CAS_WRITE_4(sc, CAS_RX_CONF, 0);
779 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_RX |
799 CAS_WRITE_4(sc, CAS_TX_CONF, 0);
806 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_TX |
821 CAS_WRITE_4(sc, CAS_MAC_RX_CONF,
836 CAS_WRITE_4(sc, CAS_MAC_TX_CONF,
1009 CAS_WRITE_4(sc, CAS_TX_DESC3_BASE_HI,
1011 CAS_WRITE_4(sc, CAS_TX_DESC3_BASE_LO,
1014 CAS_WRITE_4(sc, CAS_RX_COMP_BASE_HI,
1016 CAS_WRITE_4(sc, CAS_RX_COMP_BASE_LO,
1019 CAS_WRITE_4(sc, CAS_RX_DESC_BASE_HI,
1021 CAS_WRITE_4(sc, CAS_RX_DESC_BASE_LO,
1025 CAS_WRITE_4(sc, CAS_RX_DESC2_BASE_HI,
1027 CAS_WRITE_4(sc, CAS_RX_DESC2_BASE_LO,
1041 CAS_WRITE_4(sc, CAS_CAW, CAS_CAW_RR_DIS);
1049 CAS_WRITE_4(sc, CAS_INF_BURST,
1056 CAS_WRITE_4(sc, CAS_INTMASK,
1067 CAS_WRITE_4(sc, CAS_CLEAR_ALIAS, 0);
1068 CAS_WRITE_4(sc, CAS_MAC_RX_MASK, ~CAS_MAC_RX_OVERFLOW);
1069 CAS_WRITE_4(sc, CAS_MAC_TX_MASK,
1072 CAS_WRITE_4(sc, CAS_MAC_CTRL_MASK,
1076 CAS_WRITE_4(sc, CAS_MAC_CTRL_MASK,
1082 CAS_WRITE_4(sc, CAS_ERROR_MASK,
1087 CAS_WRITE_4(sc, CAS_BIM_CONF,
1095 CAS_WRITE_4(sc, CAS_TX_CONF, v | CAS_TX_CONF_TXDMA_EN |
1108 CAS_WRITE_4(sc, CAS_RX_CONF,
1112 CAS_WRITE_4(sc, CAS_RX_PTHRS,
1116 CAS_WRITE_4(sc, CAS_RX_BLANK,
1120 CAS_WRITE_4(sc, CAS_RX_AEMPTY_THRS,
1124 CAS_WRITE_4(sc, CAS_RX_PSZ,
1131 CAS_WRITE_4(sc, CAS_RX_RED, 0);
1135 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_ADDR, v);
1136 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_LO, 0);
1137 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_MD, 0);
1138 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_HI, 0);
1142 CAS_WRITE_4(sc, CAS_RX_CTRL_FIFO, 0);
1143 CAS_WRITE_4(sc, CAS_RX_IPP_ADDR, 0);
1146 CAS_WRITE_4(sc, CAS_RX_CONF,
1166 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, v);
1171 CAS_WRITE_4(sc, CAS_RX_KICK, CAS_NRXDESC - 4);
1172 CAS_WRITE_4(sc, CAS_RX_COMP_TAIL, 0);
1174 CAS_WRITE_4(sc, CAS_RX_KICK2, CAS_NRXDESC2 - 4);
1339 CAS_WRITE_4(sc, CAS_MAC_IPG0, 0);
1340 CAS_WRITE_4(sc, CAS_MAC_IPG1, 8);
1341 CAS_WRITE_4(sc, CAS_MAC_IPG2, 4);
1344 CAS_WRITE_4(sc, CAS_MAC_MIN_FRAME, ETHER_MIN_LEN);
1346 CAS_WRITE_4(sc, CAS_MAC_MAX_BF,
1352 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x7);
1353 CAS_WRITE_4(sc, CAS_MAC_JAM_SIZE, 0x4);
1354 CAS_WRITE_4(sc, CAS_MAC_ATTEMPT_LIMIT, 0x10);
1355 CAS_WRITE_4(sc, CAS_MAC_CTRL_TYPE, 0x8808);
1358 CAS_WRITE_4(sc, CAS_MAC_RANDOM_SEED,
1364 CAS_WRITE_4(sc, i, 0);
1367 CAS_WRITE_4(sc, CAS_MAC_ADDR42, 0x0001);
1368 CAS_WRITE_4(sc, CAS_MAC_ADDR43, 0xc200);
1369 CAS_WRITE_4(sc, CAS_MAC_ADDR44, 0x0180);
1372 CAS_WRITE_4(sc, CAS_MAC_AFILTER0, 0);
1373 CAS_WRITE_4(sc, CAS_MAC_AFILTER1, 0);
1374 CAS_WRITE_4(sc, CAS_MAC_AFILTER2, 0);
1375 CAS_WRITE_4(sc, CAS_MAC_AFILTER_MASK1_2, 0);
1376 CAS_WRITE_4(sc, CAS_MAC_AFILTER_MASK0, 0);
1381 CAS_WRITE_4(sc, i, 0);
1387 CAS_WRITE_4(sc, CAS_MAC_NORM_COLL_CNT, 0);
1388 CAS_WRITE_4(sc, CAS_MAC_FIRST_COLL_CNT, 0);
1389 CAS_WRITE_4(sc, CAS_MAC_EXCESS_COLL_CNT, 0);
1390 CAS_WRITE_4(sc, CAS_MAC_LATE_COLL_CNT, 0);
1391 CAS_WRITE_4(sc, CAS_MAC_DEFER_TMR_CNT, 0);
1392 CAS_WRITE_4(sc, CAS_MAC_PEAK_ATTEMPTS, 0);
1393 CAS_WRITE_4(sc, CAS_MAC_RX_FRAME_COUNT, 0);
1394 CAS_WRITE_4(sc, CAS_MAC_RX_LEN_ERR_CNT, 0);
1395 CAS_WRITE_4(sc, CAS_MAC_RX_ALIGN_ERR, 0);
1396 CAS_WRITE_4(sc, CAS_MAC_RX_CRC_ERR_CNT, 0);
1397 CAS_WRITE_4(sc, CAS_MAC_RX_CODE_VIOL, 0);
1400 CAS_WRITE_4(sc, CAS_MAC_SPC, 0x1BF0 << CAS_MAC_SPC_TIME_SHFT);
1403 CAS_WRITE_4(sc, CAS_MAC_ADDR0, (laddr[4] << 8) | laddr[5]);
1404 CAS_WRITE_4(sc, CAS_MAC_ADDR1, (laddr[2] << 8) | laddr[3]);
1405 CAS_WRITE_4(sc, CAS_MAC_ADDR2, (laddr[0] << 8) | laddr[1]);
1408 CAS_WRITE_4(sc, CAS_MAC_XIF_CONF, CAS_MAC_XIF_CONF_TX_OE);
1435 CAS_WRITE_4(sc, CAS_TX_KICK3, sc->sc_txnext);
1877 CAS_WRITE_4(sc, CAS_RX_COMP_TAIL, sc->sc_rxcptr);
1940 CAS_WRITE_4(sc, CAS_RX_KICK,
1982 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff);
2099 CAS_WRITE_4(sc, CAS_INTMASK,
2152 CAS_WRITE_4(sc, CAS_MIF_CONF,
2216 CAS_WRITE_4(sc, CAS_MIF_FRAME, v);
2251 CAS_WRITE_4(sc, CAS_PCS_CTRL, val);
2260 CAS_WRITE_4(sc, CAS_PCS_CONF, 0);
2263 CAS_WRITE_4(sc, CAS_PCS_ANAR, val);
2266 CAS_WRITE_4(sc, CAS_PCS_SERDES_CTRL,
2270 CAS_WRITE_4(sc, CAS_PCS_CONF,
2283 CAS_WRITE_4(sc, reg, val);
2295 CAS_WRITE_4(sc, CAS_MIF_FRAME, v);
2362 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, txcfg);
2364 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, rxcfg);
2374 CAS_WRITE_4(sc, CAS_MAC_CTRL_CONF, v);
2395 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x41);
2397 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x7);
2402 CAS_WRITE_4(sc, CAS_MAC_SLOT_TIME,
2405 CAS_WRITE_4(sc, CAS_MAC_SLOT_TIME,
2419 CAS_WRITE_4(sc, CAS_MAC_XIF_CONF, v);
2424 CAS_WRITE_4(sc, CAS_MAC_TX_CONF,
2426 CAS_WRITE_4(sc, CAS_MAC_RX_CONF,
2542 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, v);
2591 CAS_WRITE_4(sc,
2597 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, v | CAS_MAC_RX_CONF_EN);
2777 CAS_WRITE_4(sc, CAS_BIM_LDEV_OEN,
2877 CAS_WRITE_4(sc, CAS_BIM_LDEV_OEN, 0);