Lines Matching refs:REG_RD
919 uint32_t val = REG_RD(sc, reg);
928 uint32_t val = REG_RD(sc, reg);
951 REG_RD(sc, params->lfa_base +
966 link_status = REG_RD(sc, params->shmem_base +
995 saved_val = REG_RD(sc, params->lfa_base +
1004 saved_val = REG_RD(sc, params->lfa_base +
1013 saved_val = REG_RD(sc, params->lfa_base +
1023 cur_speed_cap_mask = REG_RD(sc, params->lfa_base +
1036 REG_RD(sc, params->lfa_base +
1046 eee_status = REG_RD(sc, params->shmem2_base +
1077 gp_oenable = REG_RD(sc, MCP_REG_MCPR_GP_OENABLE);
1080 *en = (REG_RD(sc, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
1094 gp_output = REG_RD(sc, MCP_REG_MCPR_GP_OUTPUTS);
1103 gp_oenable = REG_RD(sc, MCP_REG_MCPR_GP_OENABLE);
2125 val_xoff = REG_RD(sc, emac_base +
2128 val_xon = REG_RD(sc, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
2134 val_xoff = REG_RD(sc, emac_base +
2137 val_xon = REG_RD(sc, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
2173 cur_mode = REG_RD(sc, emac_base + EMAC_REG_EMAC_MDIO_MODE);
2210 port4mode_ovwr_val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
2216 return (uint8_t)REG_RD(sc, MISC_REG_PORT4MODE_EN);
2237 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
2242 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
2283 if (!(REG_RD(sc, MISC_REG_RESET_REG_2) &
2286 val = REG_RD(sc, umac_base + UMAC_REG_COMMAND_CONFIG);
2411 (REG_RD(sc, MISC_REG_RESET_REG_2) &
2465 if (REG_RD(sc, MISC_REG_RESET_REG_2) &
2471 pfc_ctrl = REG_RD(sc, xmac_base + XMAC_REG_PFC_CTRL_HI);
2477 val = REG_RD(sc, xmac_base + XMAC_REG_CTRL);
2618 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
2649 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_RX_MODE);
2678 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
2927 xcm_mask = REG_RD(sc, port ? NIG_REG_LLH1_XCM_MASK :
3037 val = REG_RD(sc, MISC_REG_RESET_REG_2);
3248 uint32_t nig_bmac_enable = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
3255 if (REG_RD(sc, MISC_REG_RESET_REG_2) &
3281 init_crd = REG_RD(sc, PBF_REG_P0_INIT_CRD + port*4);
3282 crd = REG_RD(sc, PBF_REG_P0_CREDIT + port*8);
3287 crd = REG_RD(sc, PBF_REG_P0_CREDIT + port*8);
3290 crd = REG_RD(sc, PBF_REG_P0_CREDIT + port*8);
3362 if (REG_RD(sc, NIG_REG_PORT_SWAP))
3368 if (REG_RD(sc, NIG_REG_PORT_SWAP))
3397 mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
3410 tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3433 mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
3446 val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3474 chip_id = (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) |
3475 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);
3491 val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3513 val = REG_RD(sc, phy->mdio_ctrl +
3551 chip_id = (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) |
3552 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);
3569 tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3590 tmp = REG_RD(sc, phy->mdio_ctrl +
3625 if (REG_RD(sc, params->shmem2_base) <=
3690 eee_mode = ((REG_RD(sc, params->shmem_base +
3866 board_cfg = REG_RD(sc, params->shmem_base +
3874 sfp_ctrl = REG_RD(sc, params->shmem_base +
3906 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
3923 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
3926 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
3947 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
3950 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
3961 data_array[i] = REG_RD(sc, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
4037 path_swap_ovr = REG_RD(sc, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
4041 path_swap = REG_RD(sc, MISC_REG_FOUR_PORT_PATH_SWAP);
4047 port_swap_ovr = REG_RD(sc, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
4051 port_swap = REG_RD(sc, MISC_REG_FOUR_PORT_PORT_SWAP);
4061 REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
4066 REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP);
4592 if (REG_RD(sc, params->shmem_base +
4771 cfg_tap_val = REG_RD(sc, params->shmem_base +
5085 cfg_pin = (REG_RD(sc, shmem_base +
5162 serdes_net_if = (REG_RD(sc, params->shmem_base +
5225 cfg_pin = REG_RD(sc, params->shmem_base +
5246 serdes_net_if = (REG_RD(sc, params->shmem_base +
5561 vars->link_status = REG_RD(sc, params->shmem_base +
5571 vars->eee_status = REG_RD(sc, params->shmem2_base +
5581 media_types = REG_RD(sc, sync_offset);
5599 vars->aeu_int_mask = REG_RD(sc, sync_offset);
6829 REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6831 REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6832 REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
6833 REG_RD(sc, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
6835 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6836 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6849 latch_status = REG_RD(sc,
6973 spirom_ver = REG_RD(sc, params->phy[ELINK_EXT_PHY1].ver_addr);
6983 spirom_ver = REG_RD(sc, params->phy[ELINK_EXT_PHY2].ver_addr);
7012 md_devad = REG_RD(sc, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
7582 REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
7584 is_mi_int = (uint8_t)(REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
7587 REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
7589 REG_RD(sc, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
7592 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
7593 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
8166 if (REG_RD(sc, params->shmem_base +
8526 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
8527 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
8541 tx_en_mode = REG_RD(sc, params->shmem_base +
8673 pin_cfg = (REG_RD(sc, params->shmem_base +
8970 media_types = REG_RD(sc, sync_offset);
9015 val = REG_RD(sc, params->shmem_base +
9280 uint32_t fault_led_gpio = REG_RD(sc, params->shmem_base +
9313 pin_cfg = (REG_RD(sc, params->shmem_base +
9435 uint32_t val = REG_RD(sc, params->shmem_base +
9729 tx_en_mode = REG_RD(sc, params->shmem_base +
9977 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
9978 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
10102 tx_en_mode = REG_RD(sc, params->shmem_base +
10132 uint32_t val = REG_RD(sc, params->shmem_base +
10753 pair_swap = REG_RD(sc, params->shmem_base +
10783 reset_pin[idx] = REG_RD(sc, shmem_base_path[idx] +
10796 reset_pin[idx] = REG_RD(sc, shmem_base_path[idx] +
10815 uint32_t other_shmem_base_addr = REG_RD(sc, params->shmem2_base +
10994 uint32_t cms_enable = REG_RD(sc, params->shmem_base +
11330 if (REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 +
11398 if (REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 +
11565 cfg_pin = (REG_RD(sc, params->shmem_base +
11806 cfg_pin = (REG_RD(sc, params->shmem_base +
12638 rx = REG_RD(sc, shmem_base +
12642 tx = REG_RD(sc, shmem_base +
12646 rx = REG_RD(sc, shmem_base +
12650 tx = REG_RD(sc, shmem_base +
12669 ext_phy_config = REG_RD(sc, shmem_base +
12674 ext_phy_config = REG_RD(sc, shmem_base +
12690 uint32_t switch_cfg = (REG_RD(sc, shmem_base +
12694 chip_id = (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) |
12695 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);
12700 phy_addr = REG_RD(sc,
12703 if (REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
12708 serdes_net_if = (REG_RD(sc, shmem_base +
12791 phy_addr = REG_RD(sc,
12797 phy_addr = REG_RD(sc,
12902 config2 = REG_RD(sc, shmem_base + offsetof(struct shmem_region,
12913 uint32_t size = REG_RD(sc, shmem2_base);
12936 uint32_t raw_ver = REG_RD(sc, phy->ver_addr);
12970 link_config = REG_RD(sc, params->shmem_base +
12973 phy->speed_cap_mask = REG_RD(sc, params->shmem_base +
12978 link_config = REG_RD(sc, params->shmem_base +
12981 phy->speed_cap_mask = REG_RD(sc, params->shmem_base +
13121 media_types = REG_RD(sc, sync_offset);
13505 lfa_sts = REG_RD(sc, params->lfa_base +
13584 tmp_val = REG_RD(sc, params->lfa_base +
13592 lfa_sts = REG_RD(sc, params->lfa_base +
13811 if (REG_RD(sc, MISC_REG_RESET_REG_2) &
13886 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
13887 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
14011 val = REG_RD(sc, MISC_REG_GPIO_EVENT_EN);
14054 uint32_t phy_gpio_reset = REG_RD(sc, shmem_base +
14106 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
14107 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
14282 val = REG_RD(sc, MISC_REG_GEN_PURP_HWG);
14286 phy_ver = REG_RD(sc, shmem_base_path[0] +
14318 cfg_pin = (REG_RD(sc, params->shmem_base +
14433 (REG_RD(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port*4)))
14437 (REG_RD(sc, MISC_REG_RESET_REG_2) &
14451 if (REG_RD(sc, mac_base + XMAC_REG_RX_LSS_STATUS))
14457 } else if (REG_RD(sc, MISC_REG_RESET_REG_2) &
14488 cfg_pin = (REG_RD(sc, params->shmem_base + offsetof(struct shmem_region,
14629 if ((REG_RD(sc, params->shmem_base +
14729 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
14730 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
14750 aeu_mask = REG_RD(sc, offset);
14755 val = REG_RD(sc, MISC_REG_GPIO_EVENT_EN);