Lines Matching refs:port
968 port_mb[params->port].link_status));
1048 eee_status[params->port]));
1232 const uint8_t port = params->port;
1236 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
1238 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
1240 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
1242 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
1244 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
1246 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
1249 if (!port) {
1270 const uint8_t port = params->port;
1277 if (port) {
1287 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
1292 if (port) {
1310 if (port)
1315 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
1319 * for here is note appropriate.In 2 port mode port0 only COS0-5
1321 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
1324 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
1326 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
1328 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
1330 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
1332 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
1334 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
1336 if (!port) {
1356 const uint8_t port = params->port;
1360 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
1361 * port mode port1 has COS0-2 that can be used for WFQ.
1363 if (!port) {
1386 const uint8_t port = params->port;
1396 if (port)
1404 if (port)
1411 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
1415 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
1418 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
1420 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.
1421 * In 4 port mode port1 has COS0-2 that can be used for WFQ.
1423 if (!port) {
1493 const uint8_t port = params->port;
1499 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
1502 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
1505 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
1509 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
1527 const uint8_t port)
1538 (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
1540 pbf_reg_adress_crd_weight = (port) ?
1544 nig_reg_adress_crd_weight = (port) ?
1547 pbf_reg_adress_crd_weight = (port) ?
1551 nig_reg_adress_crd_weight = (port) ?
1555 pbf_reg_adress_crd_weight = (port) ?
1559 if (port)
1567 if (port)
1574 if (port)
1659 const uint8_t port = params->port;
1660 const uint8_t max_num_of_cos = (port) ? ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 :
1741 const uint8_t port = params->port;
1747 const uint8_t max_num_of_cos = (port) ? ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 :
1804 if (port) {
1835 const uint8_t port = params->port;
1842 const uint8_t max_num_of_cos = (port) ? ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 :
1887 port);
2059 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
2118 uint32_t emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2209 /* Check 4-port override enabled */
2212 /* Return 4-port mode override value */
2215 /* Return 4-port mode from input pin */
2224 uint8_t port = params->port;
2225 uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2230 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
2233 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
2270 REG_WR(sc, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
2272 REG_WR(sc, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
2274 REG_WR(sc, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
2280 uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
2284 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
2301 uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
2305 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
2309 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
2314 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
2401 /* In 4-port mode, need to set the mode only once, so if XMAC is
2414 "XMAC already out of reset in 4-port mode\n");
2438 "Init XMAC to 10G x 1 port per path\n");
2460 uint8_t port = params->port;
2462 uint32_t pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
2476 ELINK_DEBUG_P1(sc, "Disable XMAC on port %x\n", port);
2493 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
2504 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
2560 uint8_t port = params->port;
2561 uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2568 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2571 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
2577 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
2578 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
2588 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
2589 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
2600 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
2602 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
2607 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
2686 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port*4, 1);
2694 REG_WR(sc, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
2697 REG_WR(sc, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
2698 REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
2699 REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
2702 REG_WR(sc, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
2709 REG_WR(sc, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
2710 REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
2716 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2719 REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2722 REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
2733 uint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
2766 uint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
2849 uint32_t priority_mask, uint8_t port)
2855 nig_reg_rx_priority_mask_add = (port) ?
2860 nig_reg_rx_priority_mask_add = (port) ?
2865 nig_reg_rx_priority_mask_add = (port) ?
2870 if (port)
2875 if (port)
2880 if (port)
2896 port_mb[params->port].link_status), link_status);
2906 link_attr_sync[params->port]), link_attr);
2917 uint8_t port = params->port;
2927 xcm_mask = REG_RD(sc, port ? NIG_REG_LLH1_XCM_MASK :
2940 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2952 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2958 REG_WR(sc, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2960 REG_WR(sc, port ? NIG_REG_LLFC_OUT_EN_1 :
2962 REG_WR(sc, port ? NIG_REG_LLFC_ENABLE_1 :
2964 REG_WR(sc, port ? NIG_REG_PAUSE_ENABLE_1 :
2967 REG_WR(sc, port ? NIG_REG_PPP_ENABLE_1 :
2970 REG_WR(sc, port ? NIG_REG_LLH1_XCM_MASK :
2973 REG_WR(sc, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :
2977 REG_WR(sc, port ? NIG_REG_XCM1_OUT_EN :
2981 REG_WR(sc, port ? NIG_REG_P1_HWPFC_ENABLE :
2990 nig_params->rx_cos_priority_mask[i], port);
2992 REG_WR(sc, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
2996 REG_WR(sc, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
3000 REG_WR(sc, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
3039 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
3055 REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
3065 uint8_t port = params->port;
3066 uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
3138 uint8_t port = params->port;
3139 uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
3203 uint8_t port = params->port;
3209 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
3214 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
3217 REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
3224 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
3225 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
3226 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
3232 REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
3233 REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
3234 REG_WR(sc, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
3235 REG_WR(sc, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
3236 REG_WR(sc, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
3237 REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
3243 static void elink_set_bmac_rx(struct bxe_softc *sc, uint32_t chip_id, uint8_t port, uint8_t en)
3245 uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
3248 uint32_t nig_bmac_enable = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
3256 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
3273 uint8_t port = params->port;
3277 /* Disable port */
3278 REG_WR(sc, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
3281 init_crd = REG_RD(sc, PBF_REG_P0_INIT_CRD + port*4);
3282 crd = REG_RD(sc, PBF_REG_P0_CREDIT + port*8);
3287 crd = REG_RD(sc, PBF_REG_P0_CREDIT + port*8);
3290 crd = REG_RD(sc, PBF_REG_P0_CREDIT + port*8);
3302 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
3304 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port*4, 0);
3311 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
3313 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port*4, thresh);
3325 REG_WR(sc, PBF_REG_P0_INIT_CRD + port*4, init_crd);
3330 REG_WR(sc, PBF_REG_INIT_P0 + port*4, 0x1);
3332 REG_WR(sc, PBF_REG_INIT_P0 + port*4, 0x0);
3334 /* Enable port */
3335 REG_WR(sc, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
3344 * @port: port id
3347 * emac1) depend on the mdc_mdio_access, port, port swapped. Each
3355 uint32_t mdc_mdio_access, uint8_t port)
3374 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3377 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
3626 offsetof(struct shmem2_region, eee_status[params->port]))
3692 port_feature_config[params->port].
3713 REG_WR(sc, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2),
3763 REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0);
3780 REG_WR(sc, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);
3806 eee_status[params->port]), eee_status);
3864 uint8_t port = params->port;
3876 dev_info.port_hw_config[port].e3_cmn_pin_cfg));
4028 uint8_t path, port;
4031 port = params->port;
4046 /* Figure out port swap value */
4054 port = port ^ 1;
4056 lane = (port<<1) + path;
4057 } else { /* Two port mode - no port swap */
4113 static void elink_set_serdes_access(struct bxe_softc *sc, uint8_t port)
4115 uint32_t emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
4118 REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
4124 REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
4127 static void elink_serdes_deassert(struct bxe_softc *sc, uint8_t port)
4133 val = ELINK_SERDES_RESET_BITS << (port*16);
4140 elink_set_serdes_access(sc, port);
4142 REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
4154 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0);
4155 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,
4164 uint8_t port;
4167 port = params->port;
4169 val = ELINK_XGXS_RESET_BITS << (port*16);
4594 port_hw_config[params->port].default_cfg)) &
4773 port_hw_config[params->port].
5078 uint32_t shmem_base, uint8_t port,
5087 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
5109 *gpio_port = port;
5122 params->shmem_base, params->port,
5164 port_hw_config[params->port].default_cfg)) &
5223 uint8_t port = params->port;
5227 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
5248 port_hw_config[params->port].default_cfg)) &
5556 uint8_t port = params->port;
5563 port_mb[port].link_status));
5573 eee_status[params->port]));
5580 dev_info.port_hw_config[port].media_type);
5597 dev_info.port_hw_config[port].aeu_int_mask);
5611 link_attr_sync[params->port]);
5658 elink_set_serdes_access(sc, params->port);
5676 elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized,"
6101 ELINK_DEBUG_P1(sc, "1G parallel detect link on port %d\n",
6102 params->port);
6112 ELINK_DEBUG_P1(sc, "10G parallel detect link on port %d\n",
6113 params->port);
6609 uint8_t port = params->port;
6613 elink_bits_dis(sc, GRCBASE_EMAC0 + port*0x400 +
6645 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
6784 elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized,"
6793 uint8_t port = params->port;
6824 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6827 ELINK_DEBUG_P3(sc, "port %x, is_xgxs %x, int_status 0x%x\n", port,
6829 REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6831 REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6832 REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
6833 REG_RD(sc, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
6835 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6836 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6839 static void elink_rearm_latch_signal(struct bxe_softc *sc, uint8_t port,
6850 NIG_REG_LATCH_STATUS_0 + port*8);
6856 + port*4,
6861 + port*4,
6867 REG_WR(sc, NIG_REG_LATCH_STATUS_0 + port*8,
6877 uint8_t port = params->port;
6882 elink_bits_dis(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6908 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
7002 uint8_t port = params->port;
7013 port*0x18));
7015 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
7036 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
7057 uint8_t port = params->port;
7062 uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
7064 ELINK_DEBUG_P2(sc, "elink_set_led: port %x, mode %d\n", port, mode);
7083 REG_WR(sc, NIG_REG_LED_10G_P0 + port*4, 0);
7084 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4,
7114 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4, 0);
7115 REG_WR(sc, NIG_REG_LED_10G_P0 + port*4, 1);
7135 REG_WR(sc, NIG_REG_LED_10G_P0 + port*4, 1);
7140 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4, 0);
7142 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4,
7147 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4, 0);
7161 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4,
7165 REG_WR(sc, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
7168 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
7171 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
7174 port*4, 1);
7186 + port*4, 1);
7188 port*4, 0);
7190 port*4, 1);
7367 params->port*4,
7380 (0x1ff << (params->port*16)));
7392 gpio_port = params->port;
7406 uint8_t port = params->port;
7408 ELINK_DEBUG_P1(sc, "Port %x: Link is down\n", port);
7420 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
7424 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port*4, 0);
7430 elink_set_bmac_rx(sc, params->chip_id, params->port, 0);
7434 REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2),
7436 REG_WR(sc, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2),
7454 uint8_t phy_idx, port = params->port;
7486 (params->port << 2), 1);
7489 (params->port << 2), 0xfc20);
7524 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
7555 uint8_t port = params->port;
7580 ELINK_DEBUG_P3(sc, "port %x, XGXS?%x, int_status 0x%x\n",
7581 port, (vars->phy_flags & PHY_XGXS_FLAG),
7582 REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
7585 port*0x18) > 0);
7587 REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
7589 REG_RD(sc, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
7592 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
7593 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
7597 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port*4, 0);
7715 elink_rearm_latch_signal(sc, port,
7738 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
7806 void elink_ext_phy_hw_reset(struct bxe_softc *sc, uint8_t port)
7809 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
7812 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
7815 static void elink_save_spirom_version(struct bxe_softc *sc, uint8_t port,
7818 ELINK_DEBUG_P3(sc, "FW version 0x%x:0x%x for port %d\n",
7819 (uint16_t)(spirom_ver>>16), (uint16_t)spirom_ver, port);
7827 uint8_t port)
7835 elink_save_spirom_version(sc, port, (uint32_t)(fw_ver1<<16 | fw_ver2),
7894 uint8_t port)
7900 /* Boot port from external ROM */
7937 "elink_8073_8727_external_rom_boot port %x:"
7939 port, fw_ver1);
7960 elink_save_bcm_spirom_ver(sc, phy, port);
7963 "elink_8073_8727_external_rom_boot port %x:"
7965 port, fw_ver1);
8131 gpio_port = params->port;
8168 port_hw_config[params->port].default_cfg)) &
8351 ELINK_DEBUG_P1(sc, "port %x: External link up in 10G\n",
8352 params->port);
8356 ELINK_DEBUG_P1(sc, "port %x: External link up in 2.5G\n",
8357 params->port);
8361 ELINK_DEBUG_P1(sc, "port %x: External link up in 1G\n",
8362 params->port);
8365 ELINK_DEBUG_P1(sc, "port %x: External link is down\n",
8366 params->port);
8420 gpio_port = params->port;
8421 ELINK_DEBUG_P1(sc, "Setting 8073 port %d into low power mode\n",
8439 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8441 elink_ext_phy_hw_reset(sc, params->port);
8454 elink_save_spirom_version(sc, params->port, params->shmem_base, 0);
8525 gpio_port = params->port;
8536 uint8_t port = params->port;
8543 dev_info.port_hw_config[port].sfp_ctrl)) &
8545 ELINK_DEBUG_P3(sc, "Setting transmitter tx_en=%x for port %x "
8546 "mode = %x\n", tx_en, port, tx_en_mode);
8675 dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
8936 gport = params->port;
8942 (params->port << 1);
8945 // " Current SFP module in port %d is not"
8969 dev_info.port_hw_config[params->port].media_type);
9017 port_feature_config[params->port].config));
9071 elink_cb_event_log(sc, ELINK_LOG_ID_UNQUAL_IO_MODULE, params->port, vendor_name, vendor_pn); // "Warning: Unqualified SFP+ module detected,"
9282 dev_info.port_hw_config[params->port].sfp_ctrl)) &
9296 "pin %x port %x mode %x\n",
9311 uint8_t port = params->port;
9315 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
9437 port_feature_config[params->port].config));
9440 ELINK_DEBUG_P1(sc, "SFP+ module plugged in/out detected on port %d\n",
9441 params->port);
9497 params->port, &gpio_num, &gpio_port) ==
9649 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9651 elink_ext_phy_hw_reset(sc, params->port);
9723 elink_save_bcm_spirom_ver(sc, phy, params->port);
9731 dev_info.port_hw_config[params->port].sfp_ctrl))
9799 elink_save_bcm_spirom_ver(sc, phy, params->port);
9912 ELINK_DEBUG_P1(sc, "elink_8726_link_reset port %d\n", params->port);
9972 uint8_t port;
9973 /* The PHY reset is controlled by GPIO 1. Fake the port number
9979 port = (swap_val && swap_override) ^ 1;
9981 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
10104 dev_info.port_hw_config[params->port].sfp_ctrl))
10134 port_feature_config[params->port].
10218 uint8_t link_up = 0, oc_port = params->port;
10259 oc_port = SC_PATH(sc) + (params->port << 1);
10261 "8727 Power fault has been detected on port %d\n",
10319 ELINK_DEBUG_P1(sc, "port %x: External link up in 10G\n",
10320 params->port);
10324 ELINK_DEBUG_P1(sc, "port %x: External link up in 1G\n",
10325 params->port);
10328 ELINK_DEBUG_P1(sc, "port %x: External link is down\n",
10329 params->port);
10390 uint8_t port)
10405 elink_save_spirom_version(sc, port, fw_ver1 & 0xfff,
10423 elink_save_spirom_version(sc, port, 0,
10442 elink_save_spirom_version(sc, port, 0,
10452 elink_save_spirom_version(sc, port, (fw_ver2<<16) | fw_ver1,
10507 elink_save_848xx_spirom_version(phy, sc, params->port);
10513 elink_bits_en(sc, NIG_REG_LATCH_BC_0 + params->port*4,
10675 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
10678 elink_ext_phy_hw_reset(sc, params->port);
10755 dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
10888 uint8_t port, initialize = 1;
10897 port = SC_PATH(sc);
10899 port = params->port;
10904 port);
10991 elink_save_848xx_spirom_version(phy, sc, params->port);
10996 dev_info.port_hw_config[params->port].default_cfg)) &
11220 uint8_t port;
11224 port = SC_PATH(sc);
11226 port = params->port;
11231 port);
11248 uint8_t port;
11251 port = SC_PATH(sc);
11253 port = params->port;
11258 ELINK_DEBUG_P1(sc, "Port 0x%x: LED MODE OFF\n", port);
11294 port);
11331 params->port*4) &
11339 params->port*4,
11351 ELINK_DEBUG_P1(sc, "Port 0x%x: LED MODE ON\n", port);
11399 params->port*4) &
11407 params->port*4,
11420 ELINK_DEBUG_P1(sc, "Port 0x%x: LED MODE OPER\n", port);
11553 uint8_t port;
11561 * before determining the port.
11563 port = params->port;
11567 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
11796 uint8_t port;
11803 * before determining the port.
11805 port = params->port;
11808 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
11928 uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
11955 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
11985 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
11987 elink_ext_phy_hw_reset(sc, params->port);
12010 elink_save_spirom_version(sc, params->port,
12097 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
12100 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
12627 struct elink_phy *phy, uint8_t port,
12640 dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
12644 dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
12648 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
12652 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
12664 uint8_t phy_index, uint8_t port)
12671 dev_info.port_hw_config[port].external_phy_config));
12676 dev_info.port_hw_config[port].external_phy_config2));
12685 static elink_status_t elink_populate_int_phy(struct bxe_softc *sc, uint32_t shmem_base, uint8_t port,
12692 dev_info.port_feature_config[port].link_config)) &
12710 port_hw_config[port].default_cfg)) &
12793 port * 0x10);
12799 port * 0x18);
12810 port);
12816 ELINK_DEBUG_P3(sc, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
12817 port, phy->addr, phy->mdio_ctrl);
12819 elink_populate_preemphasis(sc, shmem_base, phy, port, ELINK_INT_PHY);
12827 uint8_t port,
12833 phy_index, port);
12896 elink_populate_preemphasis(sc, shmem_base, phy, port, phy_index);
12906 port_mb[port].ext_phy_fw_version);
12919 ext_phy_fw_version2[port]);
12928 phy->mdio_ctrl = elink_get_emac_base(sc, mdc_mdio_access, port);
12943 ELINK_DEBUG_P3(sc, "phy_type 0x%x port %d found in index %d\n",
12944 phy_type, port, phy_index);
12951 uint32_t shmem2_base, uint8_t port, struct elink_phy *phy)
12956 return elink_populate_int_phy(sc, shmem_base, port, phy);
12958 port, phy);
12972 port_feature_config[params->port].link_config2));
12976 port_hw_config[params->port].speed_capability_mask2));
12980 port_feature_config[params->port].link_config));
12984 port_hw_config[params->port].speed_capability_mask));
13096 params->shmem2_base, params->port,
13120 dev_info.port_hw_config[params->port].media_type);
13260 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13322 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13346 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13365 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13391 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13406 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13456 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13469 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val);
13472 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4,
13476 REG_WR(sc, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP :
13517 params->port));
13521 params->port));
13546 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13648 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
13703 elink_serdes_deassert(sc, params->port);
13720 uint8_t phy_index, port = params->port, clear_latch_ind = 0;
13721 ELINK_DEBUG_P1(sc, "Resetting the link of port %d\n", port);
13728 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
13735 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
13739 REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port*4, 0);
13740 REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
13749 elink_set_bmac_rx(sc, params->chip_id, port, 0);
13762 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port*4, 0);
13790 elink_rearm_latch_signal(sc, port, 0);
13791 elink_bits_dis(sc, NIG_REG_LATCH_BC_0 + port*4,
13805 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
13806 REG_WR(sc, NIG_REG_BMAC0_IN_EN + port*4, 0);
13807 REG_WR(sc, NIG_REG_EMAC0_IN_EN + port*4, 0);
13809 uint32_t xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
13833 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
13840 elink_set_bmac_rx(sc, params->chip_id, params->port, 0);
13861 elink_set_bmac_rx(sc, params->chip_id, params->port, 1);
13868 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13883 int8_t port = 0;
13888 port ^= (swap_val && swap_override);
13889 elink_ext_phy_hw_reset(sc, port);
13891 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13897 port_of_path = port;
13899 shmem_base = shmem_base_path[port];
13900 shmem2_base = shmem2_base_path[port];
13904 /* Extract the ext phy address for the port */
13906 port_of_path, &phy[port]) !=
13924 port);
13927 elink_cl45_write(sc, &phy[port],
13945 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13947 port_of_path = port;
13952 phy_blk[port]->addr);
13953 if (elink_8073_8727_external_rom_boot(sc, phy_blk[port],
13958 elink_cl45_read(sc, phy_blk[port],
13963 elink_cl45_write(sc, phy_blk[port],
13975 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13978 elink_cl45_read(sc, phy_blk[port],
13982 elink_cl45_write(sc, phy_blk[port],
13988 elink_cl45_read(sc, phy_blk[port],
13991 elink_cl45_write(sc, phy_blk[port],
13997 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
14007 int8_t port;
14009 /* Use port1 because of the static port-swap */
14018 for (port = 0; port < PORT_MAX; port++) {
14026 shmem_base = shmem_base_path[port];
14027 shmem2_base = shmem2_base_path[port];
14029 /* Extract the ext phy address for the port */
14031 port, &phy) !=
14045 port);
14101 int8_t port, reset_gpio;
14110 port = 1;
14112 /* Retrieve the reset gpio/port which control the reset.
14116 (uint8_t *)&reset_gpio, (uint8_t *)&port);
14118 /* Calculate the port based on port swap */
14119 port ^= (swap_val && swap_override);
14123 port);
14126 port);
14131 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
14138 port_of_path = port;
14140 shmem_base = shmem_base_path[port];
14141 shmem2_base = shmem2_base_path[port];
14145 /* Extract the ext phy address for the port */
14147 port_of_path, &phy[port]) !=
14162 elink_cl45_write(sc, &phy[port],
14176 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
14178 port_of_path = port;
14182 phy_blk[port]->addr);
14183 if (elink_8073_8727_external_rom_boot(sc, phy_blk[port],
14187 elink_cl45_write(sc, phy_blk[port],
14232 * it for single port alone
14295 /* Read the ext_phy_type for arbitrary port(0) */
14315 uint8_t port = params->port;
14320 dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
14330 elink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT, params->port); //"Error: Power fault on Port %d has"
14385 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
14398 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
14433 (REG_RD(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port*4)))
14444 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
14458 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
14462 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
14485 uint8_t led_change, port = params->port;
14489 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
14631 port_hw_config[params->port].default_cfg))
14651 uint8_t port)
14658 port, &phy)
14674 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
14693 uint8_t port)
14701 port,
14710 shmem2_base, port, &phy)
14717 gpio_port = port;
14738 dev_info.port_hw_config[port].aeu_int_mask);
14744 if (port == 0)