altera/atse/if_atse.c

131     uint32_t val4, const char *desc, const char *f, const int l)
134 	val4 = htole32(val4);
135 	DPRINTF("[%s:%d] FIFOW %s 0x%08x = 0x%08x\n", f, l, desc, off, val4);
136 	bus_write_4(res, off, val4);
142 	uint32_t val4;
144 	val4 = le32toh(bus_read_4(res, off));
145 	DPRINTF("[%s:%d] FIFOR %s 0x%08x = 0x%08x\n", f, l, desc, off, val4);
146 	return (val4);
151 #define	ATSE_TX_DATA_WRITE(sc, val4)					\
152 	bus_write_4((sc)->atse_tx_mem_res, A_ONCHIP_FIFO_MEM_CORE_DATA, val4)
154 #define	ATSE_TX_META_WRITE(sc, val4)					\
157 	    (val4), "TXM", __func__, __LINE__)
203 		uint32_t val4;						\
205 		val4 = a_onchip_fifo_mem_core_read(			\
209 		if (val4 != 0x00)					\
213 			    val4, "RX_EVENT", __func__, __LINE__);	\
217 		uint32_t val4;						\
219 		val4 = a_onchip_fifo_mem_core_read(			\
223 		if (val4 != 0x00)					\
227 			    val4, "TX_EVENT", __func__, __LINE__);	\
270 csr_write_4(struct atse_softc *sc, uint32_t reg, uint32_t val4,
274 	val4 = htole32(val4);
276 	    "atse_mem_res", reg, reg * 4, val4);
277 	bus_write_4(sc->atse_mem_res, reg * 4, val4);
283 	uint32_t val4;
285 	val4 = le32toh(bus_read_4(sc->atse_mem_res, reg * 4));
287 	    "atse_mem_res", reg, reg * 4, val4);
288 	return (val4);
299 	uint32_t val4;
301 	val4 = htole32(val & 0x0000ffff);
303 	    "atse_mem_res", reg, (bmcr + reg) * 4, val4);
304 	bus_write_4(sc->atse_mem_res, (bmcr + reg) * 4, val4);
311 	uint32_t val4;
314 	val4 = bus_read_4(sc->atse_mem_res, (bmcr + reg) * 4);
315 	val = le32toh(val4) & 0x0000ffff;
345 	uint32_t val4, fill_level;
366 	val4 = ATSE_TX_META_READ(sc);
370 		val4 = A_ONCHIP_FIFO_MEM_CORE_SOP;
371 		val4 &= ~A_ONCHIP_FIFO_MEM_CORE_EOP;
372 		ATSE_TX_META_WRITE(sc, val4);
380 		bcopy(&sc->atse_tx_buf[sc->atse_tx_m_offset], &val4,
381 		    sizeof(val4));
382 		ATSE_TX_DATA_WRITE(sc, val4);
383 		sc->atse_tx_m_offset += sizeof(val4);
384 		c += sizeof(val4);
400 		val4 = A_ONCHIP_FIFO_MEM_CORE_EOP;
403 		val4 |= ((4 - leftm) << A_ONCHIP_FIFO_MEM_CORE_EMPTY_SHIFT);
404 		x = val4;
405 		ATSE_TX_META_WRITE(sc, val4);
408 		val4 = 0;
409 		bcopy(sc->atse_tx_buf + sc->atse_tx_m_offset, &val4, leftm);
410 		ATSE_TX_DATA_WRITE(sc, val4);
489 	uint32_t mask, val4;
506 	val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG);
507 	val4 &= ~mask;
508 	CSR_WRITE_4(sc, BASE_CFG_COMMAND_CONFIG, val4);
511 		val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG);
512 		if ((val4 & mask) == 0)
516 	if ((val4 & mask) != 0)
548 	uint32_t val4;
552 	val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG);
554 	if ((val4 & BASE_CFG_COMMAND_CONFIG_MHASH_SEL) != 0)
555 		val4 &= ~BASE_CFG_COMMAND_CONFIG_MHASH_SEL;
559 		val4 |= BASE_CFG_COMMAND_CONFIG_PROMIS_EN;
561 		val4 &= ~BASE_CFG_COMMAND_CONFIG_PROMIS_EN;
563 	CSR_WRITE_4(sc, BASE_CFG_COMMAND_CONFIG, val4);
646 	uint32_t val4;
661 	val4 = atse_ethernet_option_bits[0] << 24;
662 	val4 |= atse_ethernet_option_bits[1] << 16;
663 	val4 |= atse_ethernet_option_bits[2] << 8;
664 	val4 |= atse_ethernet_option_bits[3];
666 	if (val4 != le32toh(0x00005afe)) {
669 		     val4);
793 	uint32_t val4, mask;
838 	val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG);
839 	val4 &= ~mask;
841 	CSR_WRITE_4(sc, BASE_CFG_COMMAND_CONFIG, val4);
844 		val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG);
845 		if ((val4 & mask) == 0)
849 	if ((val4 & mask) != 0) {
879 	val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG);
888 	val4 |= BASE_CFG_COMMAND_CONFIG_ETH_SPEED;
890 	val4 &= ~BASE_CFG_COMMAND_CONFIG_ETH_SPEED;
892 	val4 &= ~BASE_CFG_COMMAND_CONFIG_ENA_10;
899 	val4 |= BASE_CFG_COMMAND_CONFIG_TX_ADDR_INS;
901 	val4 |= BASE_CFG_COMMAND_CONFIG_PAD_EN;
902 	val4 &= ~BASE_CFG_COMMAND_CONFIG_CRC_FWD;
904 	val4 |= BASE_CFG_COMMAND_CONFIG_CNTL_FRM_ENA;
907 	val4 |= BASE_CFG_COMMAND_CONFIG_RX_ERR_DISC;
910 	CSR_WRITE_4(sc, BASE_CFG_COMMAND_CONFIG, val4);
917 	val4 = CSR_READ_4(sc, TX_CMD_STAT);
918 	val4 &= ~(TX_CMD_STAT_OMIT_CRC|TX_CMD_STAT_TX_SHIFT16);
919 	CSR_WRITE_4(sc, TX_CMD_STAT, val4);
920 	val4 = CSR_READ_4(sc, RX_CMD_STAT);
921 	val4 &= ~RX_CMD_STAT_RX_SHIFT16;
922 	CSR_WRITE_4(sc, RX_CMD_STAT, val4);
925 	val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG);
926 	val4 |= BASE_CFG_COMMAND_CONFIG_SW_RESET;
927 	CSR_WRITE_4(sc, BASE_CFG_COMMAND_CONFIG, val4);
930 		val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG);
931 		if ((val4 & BASE_CFG_COMMAND_CONFIG_SW_RESET) == 0)
935 	if ((val4 & BASE_CFG_COMMAND_CONFIG_SW_RESET) != 0) {
942 	val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG);
943 	val4 |= mask;
944 	CSR_WRITE_4(sc, BASE_CFG_COMMAND_CONFIG, val4);
947 		val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG);
948 		if ((val4 & mask) == mask)
952 	if ((val4 & mask) != mask) {
2033 	uint32_t val4;
2044 	val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG);
2054 			val4 |= BASE_CFG_COMMAND_CONFIG_ENA_10;
2055 			val4 &= ~BASE_CFG_COMMAND_CONFIG_ETH_SPEED;
2059 			val4 &= ~BASE_CFG_COMMAND_CONFIG_ENA_10;
2060 			val4 &= ~BASE_CFG_COMMAND_CONFIG_ETH_SPEED;
2064 			val4 &= ~BASE_CFG_COMMAND_CONFIG_ENA_10;
2065 			val4 |= BASE_CFG_COMMAND_CONFIG_ETH_SPEED;
2079 		val4 &= ~BASE_CFG_COMMAND_CONFIG_HD_ENA;
2081 		val4 |= BASE_CFG_COMMAND_CONFIG_HD_ENA;
2085 	val4 |= BASE_CFG_COMMAND_CONFIG_TX_ENA;
2086 	val4 |= BASE_CFG_COMMAND_CONFIG_RX_ENA;
2088 	CSR_WRITE_4(sc, BASE_CFG_COMMAND_CONFIG, val4);