Lines Matching defs:bar1_index
493 cvmx_npei_bar1_indexx_t bar1_index;
697 bar1_index.u32 = 0;
698 bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22);
699 bar1_index.s.ca = 1; /* Not Cached */
700 bar1_index.s.end_swp = 1; /* Endian Swap mode */
701 bar1_index.s.addr_v = 1; /* Valid entry */
712 cvmx_write64_uint32((CVMX_PEXP_NPEI_BAR1_INDEXX(base) ^ addr_swizzle), bar1_index.u32);
715 bar1_index.s.addr_idx += (((1ull << 28) / 16ull) >> 22);
917 cvmx_pemx_bar1_indexx_t bar1_index;
1161 bar1_index.u64 = 0;
1162 bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22);
1163 bar1_index.s.ca = 1; /* Not Cached */
1164 bar1_index.s.end_swp = 1; /* Endian Swap mode */
1165 bar1_index.s.addr_v = 1; /* Valid entry */
1168 cvmx_write_csr(CVMX_PEMX_BAR1_INDEXX(i, pcie_port), bar1_index.u64);
1170 bar1_index.s.addr_idx += (((1ull << 28) / 16ull) >> 22);