Lines Matching defs:p_cap
685 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
713 return p_cap->halTkipMicTxRxKeySupport ? HAL_ENXIO : HAL_OK;
767 return p_cap->halTsfAddSupport ? HAL_OK : HAL_ENOTSUPP;
803 *result = p_cap->halNumAntCfg2Ghz;
806 *result = p_cap->halNumAntCfg5Ghz;
809 *result = p_cap->hal_rx_stbc_support;
812 *result = p_cap->hal_tx_stbc_support;
816 *result = p_cap->halLDPCSupport;
822 (p_cap->halTxChainMask & 0x3) != 0x3 ||
823 (p_cap->halRxChainMask & 0x3) != 0x3) ?
827 (p_cap->halTxChainMask & 0x7) != 0x7 ||
828 (p_cap->halRxChainMask & 0x7) != 0x7) ?
881 *result = p_cap->halApmEnable;
884 return (p_cap->hal_pcie_lcr_extsync_en == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP;
886 *result = p_cap->hal_pcie_lcr_offset;
924 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
929 if (! p_cap->halTkipMicTxRxKeySupport)
980 if (p_cap->halTsfAddSupport) {
2227 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
2232 p_cap->halNumAntCfg2GHz: p_cap->halNumAntCfg5GHz;
3104 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
3113 for (entry = 0 ; entry < p_cap->halKeyCacheSize; entry++) {