ath_hal/ar9300/ar9300_attach.c

2538     HAL_CAPABILITIES *p_cap = &ahpriv->ah_caps;
2541         *low = p_cap->halLow5GhzChan;
2542         *high = p_cap->halHigh5GhzChan;
2546         *low = p_cap->halLow2GhzChan;
2547         *high = p_cap->halHigh2GhzChan;
2572     HAL_CAPABILITIES *p_cap = &ahpriv->ah_caps;
2582     p_cap->halSupportsFastClock5GHz = AH_TRUE;
2584     p_cap->halIntrMitigation = AH_TRUE;
2592     p_cap->halWirelessModes = 0;
2602         p_cap->halWirelessModes |= HAL_MODE_11A |
2609         p_cap->halWirelessModes |= HAL_MODE_11B | HAL_MODE_11G |
2617     p_cap->halTxChainMask = ar9300_eeprom_get(ahp, EEP_TX_MASK);
2618     p_cap->halRxChainMask = ar9300_eeprom_get(ahp, EEP_RX_MASK);
2626     p_cap->halTxStreams = owl_get_ntxchains(p_cap->halTxChainMask);
2627     p_cap->halRxStreams = owl_get_ntxchains(p_cap->halRxChainMask);
2635     p_cap->halTkipMicTxRxKeySupport = AH_TRUE;
2637     p_cap->halLow2GhzChan = 2312;
2638     p_cap->halHigh2GhzChan = 2732;
2640     p_cap->halLow5GhzChan = 4920;
2641     p_cap->halHigh5GhzChan = 6100;
2643     p_cap->halCipherCkipSupport = AH_FALSE;
2644     p_cap->halCipherTkipSupport = AH_TRUE;
2645     p_cap->halCipherAesCcmSupport = AH_TRUE;
2647     p_cap->halMicCkipSupport = AH_FALSE;
2648     p_cap->halMicTkipSupport = AH_TRUE;
2649     p_cap->halMicAesCcmSupport = AH_TRUE;
2651     p_cap->halChanSpreadSupport = AH_TRUE;
2652     p_cap->halSleepAfterBeaconBroken = AH_TRUE;
2654     p_cap->halBurstSupport = AH_TRUE;
2655     p_cap->halChapTuningSupport = AH_TRUE;
2656     p_cap->halTurboPrimeSupport = AH_TRUE;
2657     p_cap->halFastFramesSupport = AH_FALSE;
2659     p_cap->halTurboGSupport = p_cap->halWirelessModes & HAL_MODE_108G;
2661 //    p_cap->hal_xr_support = AH_FALSE;
2663     p_cap->halHTSupport =
2666     p_cap->halGTTSupport = AH_TRUE;
2667     p_cap->halPSPollBroken = AH_TRUE;    /* XXX fixed in later revs? */
2668     p_cap->halNumMRRetries = 4;		/* Hardware supports 4 MRR */
2669     p_cap->halHTSGI20Support = AH_TRUE;
2670     p_cap->halVEOLSupport = AH_TRUE;
2671     p_cap->halBssIdMaskSupport = AH_TRUE;
2673     p_cap->halMcastKeySrchSupport = AH_TRUE;
2674     p_cap->halTsfAddSupport = AH_TRUE;
2677         p_cap->halTotalQueues = MS(cap_field, AR_EEPROM_EEPCAP_MAXQCU);
2679         p_cap->halTotalQueues = HAL_NUM_TX_QUEUES;
2683         p_cap->halKeyCacheSize =
2686         p_cap->halKeyCacheSize = AR_KEYTABLE_SIZE;
2688     p_cap->halFastCCSupport = AH_TRUE;
2689 //    p_cap->hal_num_mr_retries = 4;
2692     p_cap->halNumGpioPins = AR9382_MAX_GPIO_PIN_NUM;
2697         p_cap->halWowSupport = AH_TRUE;
2698         p_cap->hal_wow_match_pattern_exact = AH_TRUE;
2700             p_cap->hal_wow_pattern_match_dword = AH_TRUE;
2703         p_cap->halWowSupport = AH_FALSE;
2704         p_cap->hal_wow_match_pattern_exact = AH_FALSE;
2707     p_cap->halWowSupport = AH_TRUE;
2708     p_cap->halWowMatchPatternExact = AH_TRUE;
2710         p_cap->halWowMatchPatternExact = AH_TRUE;
2713     p_cap->halCSTSupport = AH_TRUE;
2715     p_cap->halRifsRxSupport = AH_TRUE;
2716     p_cap->halRifsTxSupport = AH_TRUE;
2719     p_cap->halRtsAggrLimit = IEEE80211_AMPDU_LIMIT_MAX;
2722     p_cap->halMfpSupport = ah->ah_config.ath_hal_mfp_support;
2724     p_cap->halForcePpmSupport = AH_TRUE;
2725     p_cap->halHwBeaconProcSupport = AH_TRUE;
2739     p_cap->halHasUapsdSupport = AH_FALSE;
2742     p_cap->halNumTxMaps = 4;
2744     p_cap->halTxDescLen = sizeof(struct ar9300_txc);
2745     p_cap->halTxStatusLen = sizeof(struct ar9300_txs);
2746     p_cap->halRxStatusLen = sizeof(struct ar9300_rxs);
2748     p_cap->halRxHpFifoDepth = HAL_HP_RXFIFO_DEPTH;
2749     p_cap->halRxLpFifoDepth = HAL_LP_RXFIFO_DEPTH;
2752     p_cap->halUseCombinedRadarRssi = AH_TRUE;
2753     p_cap->halExtChanDfsSupport = AH_TRUE;
2755     p_cap->halSpectralScanSupport = AH_TRUE;
2764         p_cap->halRfSilentSupport = AH_TRUE;
2768     p_cap->halWpsPushButtonSupport = AH_FALSE;
2771     p_cap->halBtCoexSupport = AH_TRUE;
2772     p_cap->halBtCoexApsmWar = AH_FALSE;
2775     p_cap->halGenTimerSupport = AH_TRUE;
2789             p_cap->halMciSupport = AH_FALSE;
2794             p_cap->halMciSupport = (ahp->ah_enterprise_mode &
2799                  __func__, p_cap->halMciSupport);
2802         p_cap->halMciSupport = AH_FALSE;
2806         p_cap->halRadioRetentionSupport = AH_TRUE;
2808         p_cap->halRadioRetentionSupport = AH_FALSE;
2811     p_cap->halAutoSleepSupport = AH_TRUE;
2813     p_cap->halMbssidAggrSupport = AH_TRUE;
2814 //    p_cap->hal_proxy_sta_support = AH_TRUE;
2817     p_cap->hal4kbSplitTransSupport = AH_FALSE;
2824         p_cap->halRegCap =
2830         p_cap->halRegCap =
2835     p_cap->halRegCap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
2837     p_cap->halNumAntCfg5GHz =
2839     p_cap->halNumAntCfg2GHz =
2843     p_cap->halRxStbcSupport = 1; /* number of streams for STBC recieve. */
2845         p_cap->halTxStbcSupport = 0;
2847         p_cap->halTxStbcSupport = 1;
2850     p_cap->halEnhancedDmaSupport = AH_TRUE;
2851     p_cap->halEnhancedDfsSupport = AH_TRUE;
2857     p_cap->halIsrRacSupport = AH_TRUE;
2861     p_cap->hal_wep_tkip_aggr_support = AH_TRUE;
2862     p_cap->hal_wep_tkip_aggr_num_tx_delim = 10;    /* TBD */
2863     p_cap->hal_wep_tkip_aggr_num_rx_delim = 10;    /* TBD */
2864     p_cap->hal_wep_tkip_max_ht_rate = 15;         /* TBD */
2873     p_cap->hal_cfend_fix_support = AH_FALSE;
2874     p_cap->hal_aggr_extra_delim_war = AH_FALSE;
2876     p_cap->halHasLongRxDescTsf = AH_TRUE;
2877 //    p_cap->hal_rx_desc_timestamp_bits = 32;
2878     p_cap->halRxTxAbortSupport = AH_TRUE;
2879     p_cap->hal_ani_poll_interval = AR9300_ANI_POLLINTERVAL;
2880     p_cap->hal_channel_switch_time_usec = AR9300_CHANNEL_SWITCH_TIME_USEC;
2883     p_cap->halPaprdEnabled = ar9300_eeprom_get(ahp, EEP_PAPRD_ENABLED);
2884     p_cap->halChanHalfRate =
2886     p_cap->halChanQuarterRate =
2891         p_cap->hal49GhzSupport = 1;
2893         p_cap->hal49GhzSupport = !(ahp->ah_enterprise_mode & AR_ENT_OTP_49GHZ_DISABLE);
2899         p_cap->halLDPCSupport = AH_FALSE;
2902             p_cap->hal_pcie_lcr_offset = 0x80; /*for Poseidon*/
2906             p_cap->hal_pcie_lcr_extsync_en = AH_TRUE;
2909         p_cap->halLDPCSupport = AH_TRUE;
2913     p_cap->halApmEnable = !! ar9300_eeprom_get(ahp, EEP_CHAIN_MASK_REDUCE);
2923                 p_cap->halAntDivCombSupport = AH_TRUE;
2925             p_cap->halAntDivCombSupportOrg = p_cap->halAntDivCombSupport;
2934         p_cap->halRxUsingLnaMixing = AH_TRUE;
2940         p_cap->hal_wow_gtk_offload_support    = AH_TRUE;
2941         p_cap->hal_wow_arp_offload_support    = AH_TRUE;
2942         p_cap->hal_wow_ns_offload_support     = AH_TRUE;
2943         p_cap->hal_wow_4way_hs_wakeup_support = AH_TRUE;
2944         p_cap->hal_wow_acer_magic_support     = AH_TRUE;
2945         p_cap->hal_wow_acer_swka_support      = AH_TRUE;
2947         p_cap->hal_wow_gtk_offload_support    = AH_FALSE;
2948         p_cap->hal_wow_arp_offload_support    = AH_FALSE;
2949         p_cap->hal_wow_ns_offload_support     = AH_FALSE;
2950         p_cap->hal_wow_4way_hs_wakeup_support = AH_FALSE;
2951         p_cap->hal_wow_acer_magic_support     = AH_FALSE;
2952         p_cap->hal_wow_acer_swka_support      = AH_FALSE;