arm/ti/ti_gpio.c

159  *	On OMAP3 and OMAP4 there is only one physical interrupt line per bank,
235  *	@bank: The bank to read from
243 ti_gpio_read_4(struct ti_gpio_softc *sc, unsigned int bank, bus_size_t off)
245 	return (bus_read_4(sc->sc_mem_res[bank], off));
251  *	@bank: The bank to write to
259 ti_gpio_write_4(struct ti_gpio_softc *sc, unsigned int bank, bus_size_t off,
262 	bus_write_4(sc->sc_mem_res[bank], off, val);
266 ti_gpio_intr_clr(struct ti_gpio_softc *sc, unsigned int bank, uint32_t mask)
271 	ti_gpio_write_4(sc, bank, TI_GPIO_IRQSTATUS_CLR_0, mask);
272 	ti_gpio_write_4(sc, bank, TI_GPIO_IRQSTATUS_CLR_1, mask);
274 	ti_gpio_write_4(sc, bank, TI_GPIO_CLEARIRQENABLE1, mask);
275 	ti_gpio_write_4(sc, bank, TI_GPIO_CLEARIRQENABLE2, mask);
338 	uint32_t bank = (pin / PINS_PER_BANK);
343 	if ((bank >= MAX_GPIO_BANKS) || (sc->sc_mem_res[bank] == NULL)) {
376 	uint32_t bank = (pin / PINS_PER_BANK);
381 	if ((bank >= MAX_GPIO_BANKS) || (sc->sc_mem_res[bank] == NULL)) {
413 	uint32_t bank = (pin / PINS_PER_BANK);
418 	if ((bank >= MAX_GPIO_BANKS) || (sc->sc_mem_res[bank] == NULL)) {
455 	uint32_t bank = (pin / PINS_PER_BANK);
462 	if ((bank >= MAX_GPIO_BANKS) || (sc->sc_mem_res[bank] == NULL)) {
474 	reg_val = ti_gpio_read_4(sc, bank, TI_GPIO_OE);
479 	ti_gpio_write_4(sc, bank, TI_GPIO_OE, reg_val);
504 	uint32_t bank = (pin / PINS_PER_BANK);
510 	if ((bank >= MAX_GPIO_BANKS) || (sc->sc_mem_res[bank] == NULL)) {
515 	ti_gpio_write_4(sc, bank, (value == GPIO_PIN_LOW) ? TI_GPIO_CLEARDATAOUT
542 	uint32_t bank = (pin / PINS_PER_BANK);
549 	if ((bank >= MAX_GPIO_BANKS) || (sc->sc_mem_res[bank] == NULL)) {
555 	val = ti_gpio_read_4(sc, bank, TI_GPIO_OE);
559 		*value = (ti_gpio_read_4(sc, bank, TI_GPIO_DATAIN) & mask) ? 1 : 0;
561 		*value = (ti_gpio_read_4(sc, bank, TI_GPIO_DATAOUT) & mask) ? 1 : 0;
584 	uint32_t bank = (pin / PINS_PER_BANK);
591 	if ((bank >= MAX_GPIO_BANKS) || (sc->sc_mem_res[bank] == NULL)) {
597 	val = ti_gpio_read_4(sc, bank, TI_GPIO_DATAOUT);
599 		ti_gpio_write_4(sc, bank, TI_GPIO_CLEARDATAOUT, mask);
601 		ti_gpio_write_4(sc, bank, TI_GPIO_SETDATAOUT, mask);
703 ti_gpio_bank_init(device_t dev, int bank)
712 	ti_prcm_clk_enable(GPIO0_CLK + FIRST_GPIO_BANK + bank);
719 	sc->sc_revision[bank] = ti_gpio_read_4(sc, bank, TI_GPIO_REVISION);
722 	if (sc->sc_revision[bank] != TI_GPIO_REV) {
725 		    bank, sc->sc_revision[bank]);
730 	ti_gpio_intr_clr(sc, bank, 0xffffffff);
735 		ti_scm_padconf_get_gpioflags(PINS_PER_BANK * bank + pin,
740 	ti_gpio_write_4(sc, bank, TI_GPIO_OE, reg_oe);