Lines Matching defs:MVT
75 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
76 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
77 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
80 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
81 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
83 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
86 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
87 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
91 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
92 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
93 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
99 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
102 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
103 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
104 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
105 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
106 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
107 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
110 setOperationAction(ISD::SREM, MVT::i32, Expand);
111 setOperationAction(ISD::UREM, MVT::i32, Expand);
112 setOperationAction(ISD::SREM, MVT::i64, Expand);
113 setOperationAction(ISD::UREM, MVT::i64, Expand);
116 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
117 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
118 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
119 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
120 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
121 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
122 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
123 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
126 setOperationAction(ISD::FSIN , MVT::f64, Expand);
127 setOperationAction(ISD::FCOS , MVT::f64, Expand);
128 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
129 setOperationAction(ISD::FREM , MVT::f64, Expand);
130 setOperationAction(ISD::FPOW , MVT::f64, Expand);
131 setOperationAction(ISD::FMA , MVT::f64, Legal);
132 setOperationAction(ISD::FSIN , MVT::f32, Expand);
133 setOperationAction(ISD::FCOS , MVT::f32, Expand);
134 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
135 setOperationAction(ISD::FREM , MVT::f32, Expand);
136 setOperationAction(ISD::FPOW , MVT::f32, Expand);
137 setOperationAction(ISD::FMA , MVT::f32, Legal);
139 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
145 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
150 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
153 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
154 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
156 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
157 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
161 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
162 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
163 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
164 setOperationAction(ISD::FROUND, MVT::f64, Legal);
166 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
167 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
168 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
169 setOperationAction(ISD::FROUND, MVT::f32, Legal);
173 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
174 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
175 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
176 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
177 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
178 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
179 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
180 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
183 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
184 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
186 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
187 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
191 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
192 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
195 setOperationAction(ISD::SELECT, MVT::i32, Expand);
196 setOperationAction(ISD::SELECT, MVT::i64, Expand);
197 setOperationAction(ISD::SELECT, MVT::f32, Expand);
198 setOperationAction(ISD::SELECT, MVT::f64, Expand);
201 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
202 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
205 setOperationAction(ISD::SETCC, MVT::i32, Custom);
208 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
210 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
213 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
216 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
217 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
219 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
220 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
221 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
222 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
225 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
233 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
234 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
238 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
239 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
240 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
241 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
242 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
243 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
244 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
245 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
246 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
247 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
250 setOperationAction(ISD::TRAP, MVT::Other, Legal);
253 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
254 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
257 setOperationAction(ISD::VASTART , MVT::Other, Custom);
262 setOperationAction(ISD::VAARG, MVT::i1, Promote);
263 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
264 setOperationAction(ISD::VAARG, MVT::i8, Promote);
265 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
266 setOperationAction(ISD::VAARG, MVT::i16, Promote);
267 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
268 setOperationAction(ISD::VAARG, MVT::i32, Promote);
269 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
270 setOperationAction(ISD::VAARG, MVT::Other, Expand);
273 setOperationAction(ISD::VAARG, MVT::Other, Custom);
274 setOperationAction(ISD::VAARG, MVT::i64, Custom);
277 setOperationAction(ISD::VAARG, MVT::Other, Expand);
281 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
283 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
286 setOperationAction(ISD::VAEND , MVT::Other, Expand);
287 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
288 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
289 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
290 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
293 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
296 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
299 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
300 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
301 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
302 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
303 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
304 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
305 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
306 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
307 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
308 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
309 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
310 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
314 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
315 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
316 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
317 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
320 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
323 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
326 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
332 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
333 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
334 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
335 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
338 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
339 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
340 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
341 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
346 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
348 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
350 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
351 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
352 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
355 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
356 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
357 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
363 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
364 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
365 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
373 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
377 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
379 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
381 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
383 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
385 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
387 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
430 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
431 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
432 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
442 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
444 setOperationAction(ISD::AND , MVT::v4i32, Legal);
445 setOperationAction(ISD::OR , MVT::v4i32, Legal);
446 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
447 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
448 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
449 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
450 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
451 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
452 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
453 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
454 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
455 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
456 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
457 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
459 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
460 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
461 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
462 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
464 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
465 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
468 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
469 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
472 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
473 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
474 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
476 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
477 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
479 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
480 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
481 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
482 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
485 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
486 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
487 setCondCodeAction(ISD::SETUGT, MVT::v4f32, Expand);
488 setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand);
489 setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand);
490 setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand);
492 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
493 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
497 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
498 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
501 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
502 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
503 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
504 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
691 return MVT::i32;
757 assert(N->getValueType(0) == MVT::v16i8 &&
795 assert(N->getValueType(0) == MVT::v16i8 &&
831 assert(N->getValueType(0) == MVT::v16i8 &&
928 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
931 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
935 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
938 return DAG.getTargetConstant(Val, MVT::i32);
960 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
989 return DAG.getTargetConstant(MaskVal, MVT::i32);
1006 if (N->getValueType(0) == MVT::i32)
1070 if (VT != MVT::i64)
1170 if ((CN->getValueType(0) == MVT::i32 ||
1176 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1178 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1179 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1274 if (VT != MVT::i64) {
1289 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1363 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1364 DAG.getRegister(PPC::X2, MVT::i64));
1384 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1385 DAG.getRegister(PPC::X2, MVT::i64));
1429 is64bit ? MVT::i64 : MVT::i32);
1441 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1451 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1462 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1474 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1485 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1511 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1512 DAG.getRegister(PPC::X2, MVT::i64));
1544 if (VT.bitsLT(MVT::i32)) {
1545 VT = MVT::i32;
1551 DAG.getConstant(Log2b, MVT::i32));
1552 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1589 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1590 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1594 if (VT == MVT::i64) {
1596 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1597 DAG.getConstant(1, MVT::i32));
1598 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1599 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1600 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1601 DAG.getConstant(1, MVT::i32));
1603 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1609 DAG.getConstant(1, MVT::i32));
1612 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1613 FprPtr, MachinePointerInfo(SV), MVT::i8,
1618 DAG.getConstant(8, MVT::i32));
1621 DAG.getConstant(4, MVT::i32));
1624 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1629 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1635 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1636 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1639 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1642 MVT::i32));
1651 DAG.getConstant(32, MVT::i32));
1654 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1656 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1657 MVT::i32));
1662 MVT::i8, false, false, 0);
1670 MVT::i32));
1672 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1678 MVT::i32, false, false, 0);
1692 DAG.getConstant(12, MVT::i32), 8, false, true,
1710 bool isPPC64 = (PtrVT == MVT::i64);
1723 isPPC64 ? MVT::i64 : MVT::i32);
1787 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
1788 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
1813 MVT::i8, false, false, 0);
1821 MachinePointerInfo(SV, nextOffset), MVT::i8,
1849 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
1856 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
1857 MVT &LocVT,
1883 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
1884 MVT &LocVT,
2023 case MVT::i32:
2026 case MVT::f32:
2029 case MVT::f64:
2032 case MVT::v16i8:
2033 case MVT::v8i16:
2034 case MVT::v4i32:
2035 case MVT::v4f32:
2117 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
2154 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2159 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
2167 MVT::Other, &MemOps[0], MemOps.size());
2173 // value to MVT::i64 and then truncate to the correct register size.
2179 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2182 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2185 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2277 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2278 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2333 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2334 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2387 case MVT::i32:
2388 case MVT::i64:
2391 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2393 if (ObjectVT == MVT::i32)
2395 // value to MVT::i64 and then truncate to the correct register size.
2406 case MVT::f32:
2407 case MVT::f64:
2416 if (ObjectVT == MVT::f32)
2430 case MVT::v4f32:
2431 case MVT::v4i32:
2432 case MVT::v8i16:
2433 case MVT::v16i8:
2505 MVT::Other, &MemOps[0], MemOps.size());
2525 bool isPPC64 = PtrVT == MVT::i64;
2584 case MVT::i32:
2585 case MVT::f32:
2588 case MVT::i64: // PPC64
2589 case MVT::f64:
2591 // Does MVT::i64 apply?
2594 case MVT::v4f32:
2595 case MVT::v4i32:
2596 case MVT::v8i16:
2597 case MVT::v16i8:
2629 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2630 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2666 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
2707 case MVT::i32:
2711 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2722 case MVT::i64: // PPC64
2725 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2727 if (ObjectVT == MVT::i32)
2729 // value to MVT::i64 and then truncate to the correct register size.
2741 case MVT::f32:
2742 case MVT::f64:
2753 if (ObjectVT == MVT::f32)
2767 case MVT::v4f32:
2768 case MVT::v4i32:
2769 case MVT::v8i16:
2770 case MVT::v16i8:
2855 MVT::Other, &MemOps[0], MemOps.size());
2889 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
2890 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
3047 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3078 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3099 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
3127 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3147 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3149 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3175 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3199 NodeTys.push_back(MVT::Other); // Returns a chain
3200 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3289 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3299 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3316 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3332 NodeTys.push_back(MVT::Other);
3333 NodeTys.push_back(MVT::Glue);
3352 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3437 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3464 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size());
3501 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3597 MVT ArgVT = Outs[i].VT;
3656 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3732 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3747 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3846 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3886 if (Arg.getValueType() == MVT::i32) {
3889 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
3919 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4010 case MVT::i32:
4011 case MVT::i64:
4021 case MVT::f32:
4022 case MVT::f64:
4031 if (Arg.getSimpleValueType().SimpleTy == MVT::f32) {
4055 if (Arg.getValueType() == MVT::f32) {
4066 case MVT::v4f32:
4067 case MVT::v4i32:
4068 case MVT::v8i16:
4069 case MVT::v16i8:
4089 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4125 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4136 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4179 bool isPPC64 = PtrVT == MVT::i64;
4229 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4231 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4277 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4280 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4291 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4341 case MVT::i32:
4342 case MVT::i64:
4352 case MVT::f32:
4353 case MVT::f64:
4370 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4385 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4396 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4398 case MVT::v4f32:
4399 case MVT::v4i32:
4400 case MVT::v8i16:
4401 case MVT::v16i8:
4421 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4469 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
4470 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
4484 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4573 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other,
4676 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
4684 DAG.getVTList(MVT::i32, MVT::Other),
4691 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
4727 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4728 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4730 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
4731 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
4733 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
4739 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4740 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4747 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4748 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4750 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
4760 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4761 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4763 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
4764 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
4766 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
4770 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4771 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4776 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4777 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4782 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4783 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4788 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4789 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4800 if (Src.getValueType() == MVT::f32)
4801 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
4806 case MVT::i32:
4810 dl, MVT::f64, Src);
4812 case MVT::i64:
4817 dl, MVT::f64, Src);
4822 bool i32Stack = Op.getValueType() == MVT::i32 && PPCSubTarget.hasSTFIWX() &&
4824 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
4836 DAG.getVTList(MVT::Other), Ops, array_lengthof(Ops),
4837 MVT::i32, MMO);
4844 if (Op.getValueType() == MVT::i32 && !i32Stack) {
4858 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
4866 unsigned FCFOp = (PPCSubTarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
4871 MVT FCFTy = (PPCSubTarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
4872 MVT::f32 : MVT::f64;
4874 if (Op.getOperand(0).getValueType() == MVT::i64) {
4886 if (Op.getValueType() == MVT::f32 &&
4896 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4897 SINT, DAG.getConstant(2047, MVT::i64));
4898 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
4899 Round, DAG.getConstant(2047, MVT::i64));
4900 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
4901 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4902 Round, DAG.getConstant(-2048, MVT::i64));
4912 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
4913 SINT, DAG.getConstant(53, MVT::i32));
4914 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
4915 Cond, DAG.getConstant(1, MVT::i64));
4916 Cond = DAG.getSetCC(dl, MVT::i32,
4917 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
4919 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
4922 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
4925 if (Op.getValueType() == MVT::f32 && !PPCSubTarget.hasFPCVT())
4927 MVT::f32, FP, DAG.getIntPtrConstant(0));
4931 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
4950 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
4958 dl, DAG.getVTList(MVT::f64, MVT::Other),
4959 Ops, 2, MVT::i32, MMO);
4967 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
4976 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
4983 if (Op.getValueType() == MVT::f32 && !PPCSubTarget.hasFPCVT())
4984 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
5017 MVT::f64, // return register
5018 MVT::Glue // unused in this context
5031 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
5036 DAG.getNode(ISD::AND, dl, MVT::i32,
5037 CWD, DAG.getConstant(3, MVT::i32));
5039 DAG.getNode(ISD::SRL, dl, MVT::i32,
5040 DAG.getNode(ISD::AND, dl, MVT::i32,
5041 DAG.getNode(ISD::XOR, dl, MVT::i32,
5042 CWD, DAG.getConstant(3, MVT::i32)),
5043 DAG.getConstant(3, MVT::i32)),
5044 DAG.getConstant(1, MVT::i32));
5047 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5151 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5154 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
5163 SDValue Elt = DAG.getConstant(Val, MVT::i32);
5175 EVT DestVT = MVT::Other) {
5176 if (DestVT == MVT::Other) DestVT = Op.getValueType();
5178 DAG.getConstant(IID, MVT::i32), Op);
5185 EVT DestVT = MVT::Other) {
5186 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
5188 DAG.getConstant(IID, MVT::i32), LHS, RHS);
5195 SDLoc dl, EVT DestVT = MVT::Other) {
5196 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
5198 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
5207 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5208 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
5213 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
5245 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5246 SDValue Z = DAG.getConstant(0, MVT::i32);
5247 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5273 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
5275 int Size = VT == MVT::v16i8 ? 1 : (VT == MVT::v8i16 ? 2 : 4);
5276 SDValue EltSize = DAG.getConstant(Size, MVT::i32);
5285 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5292 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5313 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5324 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5335 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5347 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5358 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5363 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5368 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5447 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
5448 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
5449 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
5568 MVT::i32));
5571 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
5636 DAG.getConstant(CompareOpc, MVT::i32));
5644 DAG.getConstant(CompareOpc, MVT::i32)
5646 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
5651 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
5652 DAG.getRegister(PPC::CR6, MVT::i32),
5675 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
5676 DAG.getConstant(8-(3-BitNo), MVT::i32));
5678 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
5679 DAG.getConstant(1, MVT::i32));
5683 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
5684 DAG.getConstant(1, MVT::i32));
5708 if (Op.getValueType() == MVT::v4i32) {
5711 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
5712 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
5718 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
5719 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
5720 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
5725 LHS, RHS, DAG, dl, MVT::v4i32);
5728 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
5732 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
5733 } else if (Op.getValueType() == MVT::v8i16) {
5736 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
5740 } else if (Op.getValueType() == MVT::v16i8) {
5745 LHS, RHS, DAG, dl, MVT::v8i16);
5746 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
5750 LHS, RHS, DAG, dl, MVT::v8i16);
5751 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
5759 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
5836 assert(N->getValueType(0) == MVT::i1 &&
5839 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
5854 if (VT == MVT::i64) {
5863 assert(N->getValueType(0) == MVT::ppcf128);
5864 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
5866 MVT::f64, N->getOperand(0),
5869 MVT::f64, N->getOperand(0),
5873 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
5877 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
5883 if (N->getOperand(0).getValueType() == MVT::ppcf128)
6106 assert(RC->hasType(MVT::i32) && "Invalid destination!");
6110 MVT PVT = getPointerTy();
6111 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6248 MVT PVT = getPointerTy();
6249 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6253 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6256 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6257 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6258 unsigned BP = (PVT == MVT::i64) ? PPC::X30 : PPC::R30;
6272 if (PVT == MVT::i64) {
6284 if (PVT == MVT::i64) {
6296 if (PVT == MVT::i64) {
6308 if (PVT == MVT::i64) {
6320 if (PVT == MVT::i64 && PPCSubTarget.isSVR4ABI()) {
6330 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
6331 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
6747 if ((VT == MVT::f32 && PPCSubTarget.hasFRES()) ||
6748 (VT == MVT::f64 && PPCSubTarget.hasFRE()) ||
6749 (VT == MVT::v4f32 && PPCSubTarget.hasAltivec())) {
6763 if (VT.getScalarType() == MVT::f64)
6809 if ((VT == MVT::f32 && PPCSubTarget.hasFRSQRTES()) ||
6810 (VT == MVT::f64 && PPCSubTarget.hasFRSQRTE()) ||
6811 (VT == MVT::v4f32 && PPCSubTarget.hasAltivec())) {
6825 if (VT.getScalarType() == MVT::f64)
7100 if (N->getOperand(0).getValueType() == MVT::i64 &&
7101 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
7103 if (Val.getValueType() == MVT::f32) {
7104 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
7108 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
7110 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
7112 if (N->getValueType(0) == MVT::f32) {
7113 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
7118 } else if (N->getOperand(0).getValueType() == MVT::i32) {
7130 N->getOperand(1).getValueType() == MVT::i32 &&
7131 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
7133 if (Val.getValueType() == MVT::f32) {
7134 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
7137 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
7146 DAG.getVTList(MVT::Other), Ops, array_lengthof(Ops),
7157 (N->getOperand(1).getValueType() == MVT::i32 ||
7158 N->getOperand(1).getValueType() == MVT::i16 ||
7161 N->getOperand(1).getValueType() == MVT::i64))) {
7164 if (BSwapOp.getValueType() == MVT::i16)
7165 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
7172 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
7185 (VT == MVT::v16i8 || VT == MVT::v8i16 ||
7186 VT == MVT::v4i32 || VT == MVT::v4f32) &&
7216 DAG, dl, MVT::v16i8);
7256 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
7259 if (BaseLoad.getValueType() != MVT::v4i32)
7260 BaseLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, BaseLoad);
7262 if (ExtraLoad.getValueType() != MVT::v4i32)
7263 ExtraLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, ExtraLoad);
7268 if (VT != MVT::v4i32)
7336 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
7339 N->getValueType(0) == MVT::i64))) {
7350 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
7351 MVT::i64 : MVT::i32, MVT::Other),
7356 if (N->getValueType(0) == MVT::i16)
7357 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
7459 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
7478 return DAG.getNode(ISD::BR, dl, MVT::Other,
7488 DAG.getConstant(CompareOpc, MVT::i32)
7490 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
7511 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
7512 DAG.getConstant(CompOpc, MVT::i32),
7513 DAG.getRegister(PPC::CR6, MVT::i32),
7537 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
7637 MVT VT) const {
7642 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
7646 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
7650 if (VT == MVT::f32 || VT == MVT::i32)
7652 if (VT == MVT::f64 || VT == MVT::i64)
7671 if (R.first && VT == MVT::i64 && PPCSubTarget.isPPC64() &&
7810 isPPC64? MVT::i64 : MVT::i32);
7829 bool isPPC64 = PtrVT == MVT::i64;
7876 return MVT::i64;
7878 return MVT::i32;
7899 if (VT == MVT::ppcf128)
7915 case MVT::f32:
7916 case MVT::f64: