Lines Matching refs:TII

764                                           const TargetInstrInfo &TII,
773 MIB = BuildMI(MBB, llvm::next(I), MI->getDebugLoc(), TII.get(Mips::TEQ))
883 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
939 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
943 BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
944 BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
947 BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
951 BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
952 BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
970 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1028 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
1030 BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
1032 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1034 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1037 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1039 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1041 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1043 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1045 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1046 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
1068 BuildMI(BB, DL, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0);
1073 BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
1074 BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes)
1076 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1080 BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
1081 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1084 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
1087 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1089 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1091 BuildMI(BB, DL, TII->get(Mips::SC), Success)
1093 BuildMI(BB, DL, TII->get(Mips::BEQ))
1104 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1106 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1108 BuildMI(BB, DL, TII->get(Mips::SLL), SllRes)
1110 BuildMI(BB, DL, TII->get(Mips::SRA), Dest)
1126 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1180 BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0);
1181 BuildMI(BB, DL, TII->get(BNE))
1188 BuildMI(BB, DL, TII->get(SC), Success)
1190 BuildMI(BB, DL, TII->get(BEQ))
1208 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1274 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
1276 BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
1278 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1280 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1283 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1285 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1287 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1289 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1291 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1292 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal)
1294 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
1296 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal)
1298 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal)
1306 BuildMI(BB, DL, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0);
1307 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1309 BuildMI(BB, DL, TII->get(Mips::BNE))
1318 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1320 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1322 BuildMI(BB, DL, TII->get(Mips::SC), Success)
1324 BuildMI(BB, DL, TII->get(Mips::BEQ))
1334 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1336 BuildMI(BB, DL, TII->get(Mips::SLL), SllRes)
1338 BuildMI(BB, DL, TII->get(Mips::SRA), Dest)