Lines Matching refs:LD

93   SDNode *SelectBaseOffsetLoad(LoadSDNode *LD, SDLoc dl);
94 SDNode *SelectIndexedLoad(LoadSDNode *LD, SDLoc dl);
95 SDNode *SelectIndexedLoadZeroExtend64(LoadSDNode *LD, unsigned Opcode,
97 SDNode *SelectIndexedLoadSignExtend64(LoadSDNode *LD, unsigned Opcode,
386 SDNode *HexagonDAGToDAGISel::SelectBaseOffsetLoad(LoadSDNode *LD, SDLoc dl) {
387 SDValue Chain = LD->getChain();
388 SDNode* Const32 = LD->getBasePtr().getNode();
392 ISD::isNormalLoad(LD)) {
394 EVT LoadedVT = LD->getMemoryVT();
415 LD->getValueType(0),
421 MemOp[0] = LD->getMemOperand();
423 ReplaceUses(LD, Result);
428 return SelectCode(LD);
432 SDNode *HexagonDAGToDAGISel::SelectIndexedLoadSignExtend64(LoadSDNode *LD,
436 SDValue Chain = LD->getChain();
437 EVT LoadedVT = LD->getMemoryVT();
438 SDValue Base = LD->getBasePtr();
439 SDValue Offset = LD->getOffset();
442 SDValue N1 = LD->getOperand(1);
458 MemOp[0] = LD->getMemOperand();
460 const SDValue Froms[] = { SDValue(LD, 0),
461 SDValue(LD, 1),
462 SDValue(LD, 2)
482 MemOp[0] = LD->getMemOperand();
484 const SDValue Froms[] = { SDValue(LD, 0),
485 SDValue(LD, 1),
486 SDValue(LD, 2)
495 return SelectCode(LD);
499 SDNode *HexagonDAGToDAGISel::SelectIndexedLoadZeroExtend64(LoadSDNode *LD,
503 SDValue Chain = LD->getChain();
504 EVT LoadedVT = LD->getMemoryVT();
505 SDValue Base = LD->getBasePtr();
506 SDValue Offset = LD->getOffset();
509 SDValue N1 = LD->getOperand(1);
530 MemOp[0] = LD->getMemOperand();
532 const SDValue Froms[] = { SDValue(LD, 0),
533 SDValue(LD, 1),
534 SDValue(LD, 2)
561 MemOp[0] = LD->getMemOperand();
563 const SDValue Froms[] = { SDValue(LD, 0),
564 SDValue(LD, 1),
565 SDValue(LD, 2)
575 return SelectCode(LD);
579 SDNode *HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, SDLoc dl) {
580 SDValue Chain = LD->getChain();
581 SDValue Base = LD->getBasePtr();
582 SDValue Offset = LD->getOffset();
586 EVT LoadedVT = LD->getMemoryVT();
590 bool zextval = (LD->getExtensionType() == ISD::ZEXTLOAD);
619 if (LD->getValueType(0) == MVT::i64 &&
620 LD->getExtensionType() == ISD::ZEXTLOAD) {
621 return SelectIndexedLoadZeroExtend64(LD, Opcode, dl);
623 if (LD->getValueType(0) == MVT::i64 &&
624 LD->getExtensionType() == ISD::SEXTLOAD) {
626 return SelectIndexedLoadSignExtend64(LD, Opcode, dl);
631 LD->getValueType(0),
635 MemOp[0] = LD->getMemOperand();
637 const SDValue Froms[] = { SDValue(LD, 0),
638 SDValue(LD, 1),
639 SDValue(LD, 2)
651 LD->getValueType(0),
658 MemOp[0] = LD->getMemOperand();
660 const SDValue Froms[] = { SDValue(LD, 0),
661 SDValue(LD, 1),
662 SDValue(LD, 2)
677 LoadSDNode *LD = cast<LoadSDNode>(N);
678 ISD::MemIndexedMode AM = LD->getAddressingMode();
682 result = SelectIndexedLoad(LD, dl);
684 result = SelectBaseOffsetLoad(LD, dl);
858 LoadSDNode *LD = cast<LoadSDNode>(MulOp0.getNode());
859 if (LD->getMemoryVT() != MVT::i32 ||
860 LD->getExtensionType() != ISD::SEXTLOAD ||
861 LD->getAddressingMode() != ISD::UNINDEXED) {
865 SDValue Chain = LD->getChain();
869 LD->getBasePtr(), TargetConst0,
884 LoadSDNode *LD = cast<LoadSDNode>(MulOp1.getNode());
885 if (LD->getMemoryVT() != MVT::i32 ||
886 LD->getExtensionType() != ISD::SEXTLOAD ||
887 LD->getAddressingMode() != ISD::UNINDEXED) {
891 SDValue Chain = LD->getChain();
895 LD->getBasePtr(), TargetConst0,
1038 LoadSDNode *LD = cast<LoadSDNode>(MulOp0.getNode());
1039 if (LD->getMemoryVT() != MVT::i32 ||
1040 LD->getExtensionType() != ISD::SEXTLOAD ||
1041 LD->getAddressingMode() != ISD::UNINDEXED) {
1045 SDValue Chain = LD->getChain();
1049 LD->getBasePtr(),
1063 LoadSDNode *LD = cast<LoadSDNode>(MulOp1.getNode());
1064 if (LD->getMemoryVT() != MVT::i32 ||
1065 LD->getExtensionType() != ISD::SEXTLOAD ||
1066 LD->getAddressingMode() != ISD::UNINDEXED) {
1070 SDValue Chain = LD->getChain();
1074 LD->getBasePtr(),