binutils/opcodes/sparc-dis.c

33 #define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9))
35 #define V9_P(insn) (((insn)->architecture & MASK_V9) != 0)
44 /* It is important that we only look at insn code bits as that is how the
191 is_delayed_branch (unsigned long insn)
195   for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
199       if ((opcode->match & insn) == opcode->match
200 	  && (opcode->lose & insn) == 0)
255   /* If one (and only one) insn isn't supported by the current architecture,
455   unsigned long insn;
502   insn = getword (buffer);
505   info->insn_type = dis_nonbranch;		/* Assume non branch insn.  */
509   for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
513       /* If the insn isn't supported by the current architecture, skip it.  */
517       if ((opcode->match & insn) == opcode->match
518 	  && (opcode->lose & insn) == 0)
539 	  if (X_RS1 (insn) != X_RD (insn)
543 	  if (X_RS2 (insn) != X_RD (insn)
603 		    reg (X_RS1 (insn));
608 		    reg (X_RS2 (insn));
612 		    reg (X_RD (insn));
619 		    freg (X_RS1 (insn));
623 		    fregx (X_RS1 (insn));
627 		    freg (X_RS2 (insn));
631 		    fregx (X_RS2 (insn));
635 		    freg (X_RD (insn));
639 		    fregx (X_RD (insn));
646 		    creg (X_RS1 (insn));
650 		    creg (X_RS2 (insn));
654 		    creg (X_RD (insn));
661 					    & ((int) X_IMM22 (insn) << 10)));
671 		        imm = X_SIMM (insn, 13);
673 			imm = X_SIMM (insn, 11);
675 			imm = X_SIMM (insn, 10);
697 		      int imm = X_IMM (insn, *s == 'X' ? 5 : 6);
707 		    (info->fprintf_func) (stream, "%ld", X_IMM (insn, 3));
712 		      int mask = X_MEMBAR (insn);
735 		    info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4;
740 		    info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4;
780 		    if (X_RS1 (insn) == 31)
782 		    else if ((unsigned) X_RS1 (insn) < 17)
784 					     v9_priv_reg_names[X_RS1 (insn)]);
790 		    if ((unsigned) X_RD (insn) < 17)
792 					     v9_priv_reg_names[X_RD (insn)]);
798 		    if ((unsigned) X_RS1 (insn) < 32)
800 					     v9_hpriv_reg_names[X_RS1 (insn)]);
806 		    if ((unsigned) X_RD (insn) < 32)
808 					     v9_hpriv_reg_names[X_RD (insn)]);
814 		    if (X_RS1 (insn) < 16 || X_RS1 (insn) > 25)
818 					     v9a_asr_reg_names[X_RS1 (insn)-16]);
822 		    if (X_RD (insn) < 16 || X_RD (insn) > 25)
826 					     v9a_asr_reg_names[X_RD (insn)-16]);
831 		      const char *name = sparc_decode_prefetch (X_RD (insn));
836 			(*info->fprintf_func) (stream, "%ld", X_RD (insn));
841 		    (*info->fprintf_func) (stream, "%%asr%ld", X_RS1 (insn));
845 		    (*info->fprintf_func) (stream, "%%asr%ld", X_RD (insn));
849 		    info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4;
855 		      (stream, "%#x", SEX (X_DISP22 (insn), 22));
859 		    info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4;
865 		      const char *name = sparc_decode_asi (X_ASI (insn));
870 			(*info->fprintf_func) (stream, "(%ld)", X_ASI (insn));
904 					   ((X_LDST_I (insn) << 8)
905 					    + X_ASI (insn)));
915 		      int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn);
976 		      && X_RD (prev_insn) == X_RS1 (insn))
983 			info->target += X_SIMM (insn, 13);
985 			info->target |= X_SIMM (insn, 13);