Lines Matching refs:r4
96 mr %r31, %r4
139 2: mflr %r4
140 addi %r4, %r4, 20
141 mtspr SPR_SRR0, %r4
156 li %r4, 0 /* Entry 0 */
157 rlwimi %r3, %r4, 16, 12, 15
176 3: mflr %r4 /* Use current address */
177 rlwinm %r4, %r4, 0, 0, 7 /* 16MB alignment mask */
178 ori %r4, %r4, (MAS3_SX | MAS3_SW | MAS3_SR)@l
179 mtspr SPR_MAS3, %r4 /* Set RPN and protection */
187 4: mflr %r4
188 rlwinm %r4, %r4, 0, 8, 31 /* Current offset from kernel load address */
190 add %r4, %r4, %r3 /* Convert to kernel virtual address */
191 addi %r4, %r4, 36
193 mtspr SPR_SRR0, %r4
221 mr %r4, %r31
300 3: mflr %r4
301 addi %r4, %r4, 20
302 mtspr SPR_SRR0, %r4
317 li %r4, 0
320 rlwimi %r3, %r4, 16, 12, 15
336 addi %r4, %r4, 1
337 cmpw %r4, %r6
348 li %r4, 0 /* Note AS=0 */
350 mtspr SPR_SRR1, %r4
442 * r4-r5 scratched
445 lis %r4, MAS0_TLBSEL1@h /* Select TLB1 */
446 rlwimi %r4, %r3, 16, 12, 15 /* Select our entry */
447 mtspr SPR_MAS0, %r4
462 * r4-r5 scratched
480 li %r4, 1 /* AS=1 */
481 rlwimi %r5, %r4, 12, 19, 19
482 li %r4, 0 /* Global mapping, TID=0 */
483 rlwimi %r5, %r4, 16, 8, 15
503 li %r4, 0 /* Start from Entry 0 */
505 rlwimi %r5, %r4, 16, 12, 15
510 cmpw %r4, %r29 /* our current entry? */
518 2: addi %r4, %r4, 1
519 cmpw %r4, %r3 /* Check if this is the last entry */
591 lis %r4, tlb0_ways@h
592 ori %r4, %r4, tlb0_ways@l
593 lwz %r4, 0(%r4)
646 cmpw %r6, %r4
676 li %r4, L1CSR0_DCE@l
677 not %r4, %r4
678 and %r3, %r3, %r4
711 li %r4, L1CSR1_ICE@l
712 not %r4, %r4
713 and %r3, %r3, %r4
740 mfsprg0 %r4
741 lwz %r4, TD_PCB(%r2)
742 stw %r3, PCB_ONFAULT(%r4)