Lines Matching refs:__BIT
40 /* __BIT(n): nth bit, where __BIT(0) == 0x1. */
41 #define __BIT(__n) \
46 ((__BIT(MAX((__m), (__n)) + 1) - 1) ^ (__BIT(MIN((__m), (__n))) - 1))
116 #define ADM5120_WDOG0_WTTR __BIT(31) /* 0: do not reset,
119 #define ADM5120_WDOG1_WDE __BIT(31) /* 0: deactivate,
129 #define ADM5120_WDOG_RSVD __BIT(15)
146 #define ADM5120_GPIO2_EW __BIT(6) /* 1: enable wait state pin,
152 #define ADM5120_GPIO2_CSX1 __BIT(5) /* 1: GPIO[3:4] act as
159 #define ADM5120_GPIO2_CSX0 __BIT(4) /* 1: GPIO[1:2] act as
170 #define ADM5120_MPMC_CONTROL_DWB __BIT(3) /* write 1 to
176 #define ADM5120_MPMC_CONTROL_LPM __BIT(2) /* 1: activate low-power
180 #define ADM5120_MPMC_CONTROL_AM __BIT(1) /* 1: address mirror:
186 #define ADM5120_MPMC_CONTROL_ME __BIT(0) /* 0: disable MPMC.
193 #define ADM5120_MPMC_STATUS_SRA __BIT(2) /* read-only
200 #define ADM5120_MPMC_STATUS_WBS __BIT(1) /* read-only
205 #define ADM5120_MPMC_STATUS_BU __BIT(0) /* read-only MPMC
221 #define ADM5120_MPMC_SC_WP __BIT(20) /* 1: write protect */
222 #define ADM5120_MPMC_SC_BE __BIT(20) /* 1: enable write buffer */
224 #define ADM5120_MPMC_SC_EW __BIT(8) /* 1: enable extended wait;
226 #define ADM5120_MPMC_SC_BLS __BIT(7) /* 0: byte line state pins
234 #define ADM5120_MPMC_SC_CCP __BIT(6) /* 0: chip select is active low,
238 #define ADM5120_MPMC_SC_PM __BIT(3) /* 0: page mode disabled,
242 #define ADM5120_MPMC_SC_RSVD3 __BIT(2)