Lines Matching refs:hldev
91 __hal_device_t *hldev = (__hal_device_t *) devh;
103 if (!(hldev->vpath_assignments & mBIT(i)))
106 status = __hal_vpath_pci_read(hldev, i,
122 * @hldev: HAL device handle.
127 __hal_device_pci_caps_list_process(__hal_device_t *hldev)
133 vxge_hal_pci_config_t *pci_config = &hldev->pci_config_space_bios;
135 vxge_assert(hldev != NULL);
140 vxge_hal_trace_log_device("hldev = 0x"VXGE_OS_STXFMT,
141 (ptr_t) hldev);
152 hldev->pci_caps.pm_cap_offset = next_ptr;
155 hldev->pci_caps.vpd_cap_offset = next_ptr;
158 hldev->pci_caps.sid_cap_offset = next_ptr;
161 hldev->pci_caps.msi_cap_offset = next_ptr;
164 hldev->pci_caps.vs_cap_offset = next_ptr;
167 hldev->pci_caps.shpc_cap_offset = next_ptr;
170 hldev->pci_e_caps = next_ptr;
173 hldev->pci_caps.msix_cap_offset = next_ptr;
214 hldev->pci_e_ext_caps.err_cap_offset = next_ptr;
217 hldev->pci_e_ext_caps.vc_cap_offset = next_ptr;
220 hldev->pci_e_ext_caps.dsn_cap_offset = next_ptr;
223 hldev->pci_e_ext_caps.pwr_budget_cap_offset = next_ptr;
241 * @hldev: HAL device handle.
247 __hal_device_pci_e_init(__hal_device_t *hldev)
253 vxge_assert(hldev != NULL);
258 vxge_hal_trace_log_device("hldev = 0x"VXGE_OS_STXFMT,
259 (ptr_t) hldev);
262 ptr_32 = (u32 *) ((void *) &hldev->pci_config_space_bios);
264 (void) __hal_vpath_pci_read(hldev,
265 hldev->first_vp_id,
271 __hal_device_pci_caps_list_process(hldev);
274 (void) __hal_vpath_pci_read(hldev,
275 hldev->first_vp_id,
280 vxge_os_pci_write16(hldev->header.pdev, hldev->header.cfgh,
284 ptr_32 = (u32 *) ((void *) &hldev->pci_config_space);
286 (void) __hal_vpath_pci_read(hldev,
287 hldev->first_vp_id,
299 * @hldev: HAL device handle.
304 __hal_device_bus_master_enable(__hal_device_t *hldev)
309 vxge_assert(hldev != NULL);
314 vxge_hal_trace_log_device("hldev = 0x"VXGE_OS_STXFMT,
315 (ptr_t) hldev);
317 (void) __hal_vpath_pci_read(hldev,
318 hldev->first_vp_id,
327 vxge_os_pci_write16(hldev->header.pdev, hldev->header.cfgh,
455 * @hldev: HAL Device object.
462 __hal_device_reg_addr_get(__hal_device_t *hldev)
468 vxge_assert(hldev);
473 vxge_hal_trace_log_device("hldev = 0x"VXGE_OS_STXFMT,
474 (ptr_t) hldev);
476 hldev->legacy_reg = (vxge_hal_legacy_reg_t *)
477 vxge_hal_device_get_legacy_reg(hldev->header.pdev,
478 hldev->header.regh0, hldev->header.bar0);
480 status = __hal_legacy_swapper_set(hldev->header.pdev,
481 hldev->header.regh0,
482 hldev->legacy_reg);
490 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
491 hldev->header.regh0,
492 &hldev->legacy_reg->toc_first_pointer);
494 hldev->toc_reg = (vxge_hal_toc_reg_t *)
495 ((void *) (hldev->header.bar0 + val64));
497 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
498 hldev->header.regh0,
499 &hldev->toc_reg->toc_common_pointer);
501 hldev->common_reg = (vxge_hal_common_reg_t *)
502 ((void *) (hldev->header.bar0 + val64));
505 (ptr_t) hldev->common_reg);
507 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
508 hldev->header.regh0,
509 &hldev->toc_reg->toc_memrepair_pointer);
511 hldev->memrepair_reg = (vxge_hal_memrepair_reg_t *)
512 ((void *) (hldev->header.bar0 + val64));
515 (ptr_t) hldev->memrepair_reg);
518 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
519 hldev->header.regh0,
520 &hldev->toc_reg->toc_pcicfgmgmt_pointer[i]);
522 hldev->pcicfgmgmt_reg[i] = (vxge_hal_pcicfgmgmt_reg_t *)
523 ((void *) (hldev->header.bar0 + val64));
525 "0x"VXGE_OS_STXFMT, i, (ptr_t) hldev->pcicfgmgmt_reg[i]);
528 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
529 hldev->header.regh0,
530 &hldev->toc_reg->toc_mrpcim_pointer);
532 hldev->mrpcim_reg = (vxge_hal_mrpcim_reg_t *)
533 ((void *) (hldev->header.bar0 + val64));
536 (ptr_t) hldev->mrpcim_reg);
540 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
541 hldev->header.regh0,
542 &hldev->toc_reg->toc_srpcim_pointer[i]);
544 hldev->srpcim_reg[i] = (vxge_hal_srpcim_reg_t *)
545 ((void *) (hldev->header.bar0 + val64));
547 (ptr_t) hldev->srpcim_reg[i]);
552 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
553 hldev->header.regh0,
554 &hldev->toc_reg->toc_vpmgmt_pointer[i]);
556 hldev->vpmgmt_reg[i] = (vxge_hal_vpmgmt_reg_t *)
557 ((void *) (hldev->header.bar0 + val64));
560 (ptr_t) hldev->vpmgmt_reg[i]);
565 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
566 hldev->header.regh0,
567 &hldev->toc_reg->toc_vpath_pointer[i]);
569 hldev->vpath_reg[i] = (vxge_hal_vpath_reg_t *)
570 ((void *) (hldev->header.bar0 + val64));
573 (ptr_t) hldev->vpath_reg[i]);
577 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
578 hldev->header.regh0,
579 &hldev->toc_reg->toc_kdfc);
583 hldev->kdfc = hldev->header.bar0 +
587 hldev->kdfc = hldev->header.bar1 +
591 hldev->kdfc = hldev->header.bar2 +
601 (ptr_t) hldev->kdfc);
603 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
604 hldev->header.regh0,
605 &hldev->toc_reg->toc_usdc);
609 hldev->usdc = hldev->header.bar0 +
613 hldev->usdc = hldev->header.bar1 +
617 hldev->usdc = hldev->header.bar2 +
627 (ptr_t) hldev->usdc);
629 status = vxge_hal_device_register_poll(hldev->header.pdev,
630 hldev->header.regh0,
631 &hldev->common_reg->vpath_rst_in_prog, 0,
648 * @hldev: HAL Device object.
654 __hal_device_id_get(__hal_device_t *hldev)
656 vxge_assert(hldev);
661 vxge_hal_trace_log_device("hldev = 0x"VXGE_OS_STXFMT,
662 (ptr_t) hldev);
664 (void) __hal_vpath_pci_read(hldev,
665 hldev->first_vp_id,
668 &hldev->header.device_id);
670 (void) __hal_vpath_pci_read(hldev,
671 hldev->first_vp_id,
674 &hldev->header.revision);
724 * @hldev: HAL Device object.
729 __hal_device_host_info_get(__hal_device_t *hldev)
734 vxge_assert(hldev);
739 vxge_hal_trace_log_device("hldev = 0x"VXGE_OS_STXFMT,
740 (ptr_t) hldev);
742 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
743 hldev->header.regh0,
744 &hldev->common_reg->host_type_assignments);
746 hldev->host_type = (u32)
749 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
750 hldev->header.regh0,
751 &hldev->common_reg->vplane_assignments);
753 hldev->srpcim_id = (u32)
756 hldev->vpath_assignments = vxge_os_pio_mem_read64(
757 hldev->header.pdev,
758 hldev->header.regh0,
759 &hldev->common_reg->vpath_assignments);
763 if (!(hldev->vpath_assignments & mBIT(i)))
766 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
767 hldev->header.regh0,
768 &hldev->common_reg->debug_assignments);
769 hldev->vh_id =
772 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
773 hldev->header.regh0,
774 &hldev->vpmgmt_reg[i]->vpath_to_func_map_cfg1);
775 hldev->func_id =
778 hldev->access_rights = __hal_device_access_rights_get(
779 hldev->host_type, hldev->func_id);
781 if (hldev->access_rights &
783 hldev->manager_up = TRUE;
785 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
786 hldev->header.regh0,
787 &hldev->vpmgmt_reg[i]->srpcim_to_vpath_wmsg);
789 hldev->manager_up = __hal_ifmsg_is_manager_up(val64);
792 hldev->first_vp_id = i;
805 * @hldev: HAL device.
821 __hal_device_t *hldev,
828 vxge_assert((hldev != NULL) && (signalling_rate != NULL) &&
834 vxge_hal_trace_log_device("hldev = 0x"VXGE_OS_STXFMT
836 "link_width = 0x"VXGE_OS_STXFMT, (ptr_t) hldev,
840 (((u8 *) &hldev->pci_config_space_bios) + hldev->pci_e_caps);
891 * @hldev: HAL device handle.
896 __hal_device_hw_initialize(__hal_device_t *hldev)
900 vxge_assert(hldev);
905 vxge_hal_trace_log_device("hldev = 0x"VXGE_OS_STXFMT,
906 (ptr_t) hldev);
908 __hal_device_pci_e_init(hldev);
911 if (__hal_device_pci_e_info_get(hldev, &hldev->header.signalling_rate,
912 &hldev->header.link_width) != VXGE_HAL_OK) {
913 hldev->header.signalling_rate =
915 hldev->header.link_width = VXGE_HAL_PCI_E_LINK_WIDTH_UNKNOWN;
924 if (hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM) {
925 status = __hal_srpcim_initialize(hldev);
928 if (hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM) {
929 status = __hal_mrpcim_initialize(hldev);
933 hldev->hw_is_initialized = 1;
934 hldev->header.terminating = 0;
960 __hal_device_t *hldev = (__hal_device_t *) devh;
970 if (!hldev->header.is_initialized) {
979 if (!(hldev->vpaths_deployed & mBIT(i)))
983 VXGE_HAL_VIRTUAL_PATH_HANDLE(&hldev->virtual_paths[i]));
1013 __hal_device_t *hldev = (__hal_device_t *) devh;
1023 if (!hldev->header.is_initialized) {
1032 if (!(hldev->vpaths_deployed & mBIT(i)))
1036 VXGE_HAL_VIRTUAL_PATH_HANDLE(&hldev->virtual_paths[i]));
1070 __hal_device_t *hldev = (__hal_device_t *) devh;
1080 if (!hldev->header.is_initialized) {
1087 if (!hldev->manager_up) {
1095 hldev, hldev->first_vp_id);
1106 if (!(hldev->vpaths_deployed & mBIT(i)))
1110 VXGE_HAL_VIRTUAL_PATH_HANDLE(&hldev->virtual_paths[i]));
1144 __hal_device_t *hldev = (__hal_device_t *) devh;
1146 vxge_assert((hldev != NULL) && (hw_status != NULL));
1154 *hw_status = vxge_os_pio_mem_read64(hldev->header.pdev,
1155 hldev->header.regh0,
1156 &hldev->common_reg->adapter_status);
1288 __hal_device_t *hldev = (__hal_device_t *) devh;
1300 adapter_status = vxge_os_pio_mem_read64(hldev->header.pdev,
1301 hldev->header.regh0,
1302 &hldev->common_reg->adapter_status);
1304 (void) __hal_vpath_pci_read(hldev,
1305 hldev->first_vp_id,
1335 __hal_device_t *hldev = (__hal_device_t *) devh;
1337 vxge_assert(hldev);
1345 vxge_hal_device_mask_all(hldev);
1349 if (!(hldev->vpaths_deployed & mBIT(i)))
1352 (void) __hal_vpath_intr_enable(&hldev->virtual_paths[i]);
1355 if ((hldev->header.config.intr_mode == VXGE_HAL_INTR_MODE_IRQLINE) ||
1356 (hldev->header.config.intr_mode == VXGE_HAL_INTR_MODE_EMULATED_INTA)) {
1358 val64 = hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_TX] |
1359 hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_RX] |
1360 hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_BMAP];
1363 vxge_os_pio_mem_write64(hldev->header.pdev,
1364 hldev->header.regh0,
1366 &hldev->common_reg->tim_int_status0);
1368 vxge_os_pio_mem_write64(hldev->header.pdev,
1369 hldev->header.regh0,
1371 &hldev->common_reg->tim_int_mask0);
1374 val32 = hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_TX] |
1375 hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_RX] |
1376 hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_BMAP];
1379 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
1380 hldev->header.regh0,
1382 &hldev->common_reg->tim_int_status1);
1384 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
1385 hldev->header.regh0,
1387 &hldev->common_reg->tim_int_mask1);
1391 vxge_os_pio_mem_read64(hldev->header.pdev,
1392 hldev->header.regh0,
1393 &hldev->common_reg->titan_general_int_status);
1395 vxge_hal_device_unmask_all(hldev);
1418 __hal_device_t *hldev = (__hal_device_t *) devh;
1420 vxge_assert(hldev);
1428 vxge_hal_device_mask_all(hldev);
1430 if ((hldev->header.config.intr_mode ==
1432 (hldev->header.config.intr_mode ==
1435 val64 = hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_TX] |
1436 hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_RX] |
1437 hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_BMAP];
1440 vxge_os_pio_mem_write64(hldev->header.pdev,
1441 hldev->header.regh0,
1443 &hldev->common_reg->tim_int_mask0);
1446 val32 = hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_TX] |
1447 hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_RX] |
1448 hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_BMAP];
1451 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
1452 hldev->header.regh0,
1454 &hldev->common_reg->tim_int_mask1);
1460 if (!(hldev->vpaths_deployed & mBIT(i)))
1463 (void) __hal_vpath_intr_disable(&hldev->virtual_paths[i]);
1466 vxge_hal_device_unmask_all(hldev);
1485 __hal_device_t *hldev = (__hal_device_t *) devh;
1487 vxge_assert(hldev);
1498 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
1499 hldev->header.regh0,
1501 &hldev->common_reg->titan_mask_all_int);
1520 __hal_device_t *hldev = (__hal_device_t *) devh;
1522 vxge_assert(hldev);
1530 if (hldev->header.config.intr_mode == VXGE_HAL_INTR_MODE_IRQLINE)
1533 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
1534 hldev->header.regh0,
1536 &hldev->common_reg->titan_mask_all_int);
1574 __hal_device_t *hldev = (__hal_device_t *) devh;
1578 vxge_assert((hldev != NULL) && (reason != NULL));
1588 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
1589 hldev->header.regh0,
1590 &hldev->common_reg->titan_general_int_status);
1605 adapter_status = vxge_os_pio_mem_read64(hldev->header.pdev,
1606 hldev->header.regh0,
1607 &hldev->common_reg->adapter_status);
1612 __hal_device_handle_error(hldev,
1623 vpath_mask = hldev->vpaths_deployed >>
1628 hldev->header.traffic_intr_cnt++;
1635 hldev->header.not_traffic_intr_cnt++;
1642 if (!(hldev->vpaths_deployed & mBIT(i)))
1646 &hldev->virtual_paths[i],
1689 __hal_device_t *hldev = (__hal_device_t *) devh;
1691 vxge_assert(hldev);
1701 if (!(hldev->vpaths_deployed & mBIT(i)))
1705 VXGE_HAL_VIRTUAL_PATH_HANDLE(&hldev->virtual_paths[i]));
1738 __hal_device_t *hldev = (__hal_device_t *) devh;
1749 vxge_hal_device_mask_all(hldev);
1751 status = vxge_hal_device_begin_irq(hldev, skip_alarms, &reason);
1753 vxge_hal_device_unmask_all(hldev);
1758 vxge_hal_device_clear_rx(hldev);
1760 status = vxge_hal_device_continue_irq(hldev);
1762 vxge_hal_device_clear_tx(hldev);
1770 vxge_hal_device_unmask_all(hldev);
1780 * @hldev: HAL device handle.
1786 __hal_device_handle_link_up_ind(__hal_device_t *hldev)
1788 vxge_assert(hldev);
1793 vxge_hal_trace_log_device_irq("hldev = 0x"VXGE_OS_STXFMT,
1794 (ptr_t) hldev);
1799 if (hldev->header.link_state == VXGE_HAL_LINK_UP) {
1805 hldev->header.link_state = VXGE_HAL_LINK_UP;
1810 hldev,
1811 hldev->header.upper_layer_data);
1821 * @hldev: HAL device handle.
1827 __hal_device_handle_link_down_ind(__hal_device_t *hldev)
1829 vxge_assert(hldev);
1834 vxge_hal_trace_log_device_irq("hldev = 0x"VXGE_OS_STXFMT,
1835 (ptr_t) hldev);
1840 if (hldev->header.link_state == VXGE_HAL_LINK_DOWN) {
1846 hldev->header.link_state = VXGE_HAL_LINK_DOWN;
1851 hldev,
1852 hldev->header.upper_layer_data);
1873 __hal_device_t *hldev = (__hal_device_t *) devh;
1875 vxge_assert(hldev);
1885 if (!(hldev->vpath_assignments & mBIT(i)))
1889 __hal_vpath_link_state_test(&hldev->virtual_paths[i]);
1913 __hal_device_t *hldev = (__hal_device_t *) devh;
1925 if (!(hldev->vpath_assignments & mBIT(i)))
1928 hldev->header.link_state = VXGE_HAL_LINK_NONE;
1931 __hal_vpath_link_state_poll(&hldev->virtual_paths[i]);
1955 __hal_device_t *hldev = (__hal_device_t *) devh;
1967 if (!(hldev->vpaths_deployed & mBIT(i)))
1971 __hal_vpath_data_rate_poll(&hldev->virtual_paths[i]);
1994 __hal_device_t *hldev = (__hal_device_t *) devh;
2006 if (!(hldev->vpaths_deployed & mBIT(i)))
2010 __hal_vpath_lag_mode_get(&hldev->virtual_paths[i]);
2024 * @hldev: HAL device
2032 __hal_device_t *hldev,
2036 vxge_assert(hldev);
2042 "hldev = 0x"VXGE_OS_STXFMT", vp_id = %d, type = %d",
2043 (ptr_t) hldev, vp_id, type);
2052 if (hldev->header.config.dump_on_unknown) {
2053 (void) vxge_hal_aux_device_dump(hldev);
2057 if (hldev->header.config.dump_on_serr) {
2058 (void) vxge_hal_aux_device_dump(hldev);
2064 if (hldev->header.config.dump_on_critical) {
2065 (void) vxge_hal_aux_device_dump(hldev);
2069 if (hldev->header.config.dump_on_eccerr) {
2070 (void) vxge_hal_aux_device_dump(hldev);
2091 (vxge_hal_device_h) hldev,
2092 hldev->header.upper_layer_data,
2114 __hal_device_t *hldev = (__hal_device_t *) devh;
2124 if (hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_TX] != 0) {
2125 vxge_os_pio_mem_write64(hldev->header.pdev,
2126 hldev->header.regh0,
2127 hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_TX],
2128 &hldev->common_reg->tim_int_mask0);
2131 if (hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_TX] != 0) {
2132 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
2133 hldev->header.regh0,
2134 hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_TX],
2135 &hldev->common_reg->tim_int_mask1);
2156 __hal_device_t *hldev = (__hal_device_t *) devh;
2166 if (hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_TX] != 0) {
2167 vxge_os_pio_mem_write64(hldev->header.pdev,
2168 hldev->header.regh0,
2169 hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_TX],
2170 &hldev->common_reg->tim_int_status0);
2173 if (hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_TX] != 0) {
2174 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
2175 hldev->header.regh0,
2176 hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_TX],
2177 &hldev->common_reg->tim_int_status1);
2196 __hal_device_t *hldev = (__hal_device_t *) devh;
2206 if (hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_TX] != 0) {
2207 vxge_os_pio_mem_write64(hldev->header.pdev,
2208 hldev->header.regh0,
2209 ~(hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_TX]),
2210 &hldev->common_reg->tim_int_mask0);
2213 if (hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_TX] != 0) {
2214 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
2215 hldev->header.regh0,
2216 ~(hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_TX]),
2217 &hldev->common_reg->tim_int_mask1);
2237 __hal_device_t *hldev = (__hal_device_t *) devh;
2247 if (hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_RX] != 0) {
2248 vxge_os_pio_mem_write64(hldev->header.pdev,
2249 hldev->header.regh0,
2250 hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_RX],
2251 &hldev->common_reg->tim_int_mask0);
2254 if (hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_RX] != 0) {
2255 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
2256 hldev->header.regh0,
2257 hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_RX],
2258 &hldev->common_reg->tim_int_mask1);
2279 __hal_device_t *hldev = (__hal_device_t *) devh;
2289 if (hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_RX] != 0) {
2290 vxge_os_pio_mem_write64(hldev->header.pdev,
2291 hldev->header.regh0,
2292 hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_RX],
2293 &hldev->common_reg->tim_int_status0);
2296 if (hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_RX] != 0) {
2297 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
2298 hldev->header.regh0,
2299 hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_RX],
2300 &hldev->common_reg->tim_int_status1);
2319 __hal_device_t *hldev = (__hal_device_t *) devh;
2329 if (hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_RX] != 0) {
2330 vxge_os_pio_mem_write64(hldev->header.pdev,
2331 hldev->header.regh0,
2332 ~(hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_RX]),
2333 &hldev->common_reg->tim_int_mask0);
2336 if (hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_RX] != 0) {
2337 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
2338 hldev->header.regh0,
2339 ~(hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_RX]),
2340 &hldev->common_reg->tim_int_mask1);
2359 __hal_device_t *hldev = (__hal_device_t *) devh;
2369 if ((hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_TX] != 0) ||
2370 (hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_RX] != 0)) {
2371 vxge_os_pio_mem_write64(hldev->header.pdev,
2372 hldev->header.regh0,
2373 (hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_TX] |
2374 hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_RX]),
2375 &hldev->common_reg->tim_int_mask0);
2378 if ((hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_TX] != 0) ||
2379 (hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_RX] != 0)) {
2380 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
2381 hldev->header.regh0,
2382 (hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_TX] |
2383 hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_RX]),
2384 &hldev->common_reg->tim_int_mask1);
2405 __hal_device_t *hldev = (__hal_device_t *) devh;
2415 if ((hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_TX] != 0) ||
2416 (hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_RX] != 0)) {
2417 vxge_os_pio_mem_write64(hldev->header.pdev,
2418 hldev->header.regh0,
2419 (hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_TX] |
2420 hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_RX]),
2421 &hldev->common_reg->tim_int_status0);
2424 if ((hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_TX] != 0) ||
2425 (hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_RX] != 0)) {
2426 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
2427 hldev->header.regh0,
2428 (hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_TX] |
2429 hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_RX]),
2430 &hldev->common_reg->tim_int_status1);
2449 __hal_device_t *hldev = (__hal_device_t *) devh;
2459 if ((hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_TX] != 0) ||
2460 (hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_RX] != 0)) {
2461 vxge_os_pio_mem_write64(hldev->header.pdev,
2462 hldev->header.regh0,
2463 ~(hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_TX] |
2464 hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_RX]),
2465 &hldev->common_reg->tim_int_mask0);
2468 if ((hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_TX] != 0) ||
2469 (hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_RX] != 0)) {
2470 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
2471 hldev->header.regh0,
2472 ~(hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_TX] |
2473 hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_RX]),
2474 &hldev->common_reg->tim_int_mask1);
2654 * @hldev: HAL device handle.
2662 * are 'IN', including @hldev. Upper-layer driver (ULD) cooperates with
2690 __hal_device_t *hldev;
2721 hldev = (__hal_device_t *) vxge_os_malloc(attr->pdev,
2724 if (hldev == NULL) {
2731 vxge_os_memzero(hldev, sizeof(__hal_device_t));
2733 hldev->header.magic = VXGE_HAL_DEVICE_MAGIC;
2735 __hal_channel_init_pending_list(hldev);
2737 vxge_hal_device_debug_set(hldev,
2742 hldev->trace_buf.size = device_config->tracebuf_size;
2743 hldev->trace_buf.data =
2744 (u8 *) vxge_os_malloc(attr->pdev, hldev->trace_buf.size);
2745 if (hldev->trace_buf.data == NULL) {
2749 hldev->trace_buf.offset = 0;
2750 hldev->trace_buf.wrapped_count = 0;
2756 (ptr_t) hldev);
2759 vxge_os_memcpy(&hldev->header.config, device_config,
2762 hldev->header.regh0 = attr->regh0;
2763 hldev->header.regh1 = attr->regh1;
2764 hldev->header.regh2 = attr->regh2;
2765 hldev->header.bar0 = attr->bar0;
2766 hldev->header.bar1 = attr->bar1;
2767 hldev->header.bar2 = attr->bar2;
2768 hldev->header.pdev = attr->pdev;
2769 hldev->header.irqh = attr->irqh;
2770 hldev->header.cfgh = attr->cfgh;
2772 if ((status = __hal_device_reg_addr_get(hldev)) != VXGE_HAL_OK) {
2775 vxge_hal_device_terminate(hldev);
2779 __hal_device_id_get(hldev);
2781 __hal_device_host_info_get(hldev);
2788 if (!(hldev->vpath_assignments & mBIT(i)))
2819 if (__hal_blockpool_create(hldev,
2820 &hldev->block_pool,
2830 vxge_hal_device_terminate(hldev);
2835 status = __hal_device_hw_initialize(hldev);
2840 vxge_hal_device_terminate(hldev);
2844 hldev->dump_buf = (char *) vxge_os_malloc(hldev->header.pdev,
2846 if (hldev->dump_buf == NULL) {
2852 vxge_hal_device_terminate(hldev);
2856 hldev->header.is_initialized = 1;
2858 *devh = hldev;
2876 __hal_device_t *hldev = (__hal_device_t *) devh;
2879 vxge_assert(hldev != NULL);
2880 vxge_assert(hldev->header.magic == VXGE_HAL_DEVICE_MAGIC);
2888 hldev->header.terminating = 1;
2889 hldev->header.is_initialized = 0;
2890 hldev->in_poll = 0;
2891 hldev->header.magic = VXGE_HAL_DEVICE_DEAD;
2893 if (hldev->dump_buf) {
2894 vxge_os_free(hldev->header.pdev, hldev->dump_buf,
2896 hldev->dump_buf = NULL;
2899 if (hldev->srpcim != NULL)
2900 (void) __hal_srpcim_terminate(hldev);
2902 if (hldev->mrpcim != NULL)
2903 (void) __hal_mrpcim_terminate(hldev);
2905 __hal_channel_destroy_pending_list(hldev);
2908 __hal_blockpool_destroy(&hldev->block_pool);
2911 if (hldev->trace_buf.size) {
2913 hldev->trace_buf.data,
2914 hldev->trace_buf.size);
2918 vxge_os_free(hldev->header.pdev, hldev, sizeof(__hal_device_t));
2936 __hal_device_t *hldev = (__hal_device_t *) devh;
2946 if (!hldev->hw_is_initialized) {
2948 status = __hal_device_hw_initialize(hldev);
2956 __hal_device_bus_master_enable(hldev);
2995 __hal_device_t *hldev = (__hal_device_t *) devh;
3026 __hal_device_t *hldev = (__hal_device_t *) devh;
3036 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
3037 hldev->header.regh0,
3038 &hldev->common_reg->stats_cfg0);
3042 if (!(hldev->vpaths_deployed & mBIT(i)))
3045 vxge_os_memcpy(hldev->virtual_paths[i].hw_stats_sav,
3046 hldev->virtual_paths[i].hw_stats,
3048 if (hldev->header.config.stats_read_method ==
3054 &hldev->virtual_paths[i],
3055 hldev->virtual_paths[i].hw_stats);
3060 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
3061 hldev->header.regh0,
3063 &hldev->common_reg->stats_cfg0);
3087 __hal_device_t *hldev = (__hal_device_t *) devh;
3097 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
3098 hldev->header.regh0,
3099 &hldev->common_reg->stats_cfg0);
3103 if (!(hldev->vpaths_deployed & mBIT(i)))
3110 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
3111 hldev->header.regh0,
3113 &hldev->common_reg->stats_cfg0);
3138 __hal_device_t *hldev = (__hal_device_t *) devh;
3149 if (hldev->header.config.stats_read_method ==
3154 if (!(hldev->vpaths_deployed & mBIT(i)))
3162 status = vxge_hal_device_register_poll(hldev->header.pdev,
3163 hldev->header.regh0,
3164 &hldev->common_reg->stats_cfg0,
3167 hldev->header.config.device_poll_millis);
3173 &hldev->stats.hw_dev_info_stats,
3197 __hal_device_t *hldev = (__hal_device_t *) devh;
3199 vxge_assert((hldev != NULL) && (sw_stats != NULL));
3209 &hldev->stats.sw_dev_info_stats,
3232 __hal_device_t *hldev = (__hal_device_t *) devh;
3234 vxge_assert((hldev != NULL) && (stats != NULL));
3244 &hldev->stats,
3266 __hal_device_t *hldev = (__hal_device_t *) devh;
3268 vxge_assert((hldev != NULL) && (xmac_stats != NULL));
3280 if (!(hldev->vpaths_deployed & mBIT(i)))
3283 status = __hal_vpath_xmac_tx_stats_get(&hldev->virtual_paths[i],
3292 status = __hal_vpath_xmac_rx_stats_get(&hldev->virtual_paths[i],
3325 __hal_device_t *hldev = (__hal_device_t *) devh;
3328 if (hldev == NULL)
3331 offset = hldev->trace_buf.offset;
3335 u32 leftsize = hldev->trace_buf.size - offset;
3338 vxge_os_memzero(hldev->trace_buf.data + offset,
3341 hldev->trace_buf.wrapped_count++;
3344 vxge_os_memcpy(hldev->trace_buf.data + offset,
3347 hldev->trace_buf.offset = offset;
3361 __hal_device_t *hldev = (__hal_device_t *) devh;
3364 if (hldev == NULL)
3367 offset = hldev->trace_buf.offset;
3371 if (hldev->trace_buf.wrapped_count) {
3372 for (i = hldev->trace_buf.offset;
3373 i < hldev->trace_buf.size; i += offset) {
3374 if (*(hldev->trace_buf.data + i))
3375 vxge_os_printf(hldev->trace_buf.data + i);
3376 offset = vxge_os_strlen(hldev->trace_buf.data + i) + 1;
3380 for (i = 0; i < hldev->trace_buf.offset; i += offset) {
3381 if (*(hldev->trace_buf.data + i))
3382 vxge_os_printf(hldev->trace_buf.data + i);
3383 offset = vxge_os_strlen(hldev->trace_buf.data + i) + 1;
3410 __hal_device_t *hldev = (__hal_device_t *) devh;
3416 if (hldev == NULL)
3419 offset = hldev->trace_buf.offset;
3421 if (hldev->trace_buf.wrapped_count) {
3422 for (i = hldev->trace_buf.offset;
3423 i < hldev->trace_buf.size; i += offset) {
3424 if (*(hldev->trace_buf.data + i)) {
3426 hldev->trace_buf.data + i);
3428 hldev->trace_buf.data + i) + 1;
3432 offset = vxge_os_strlen(hldev->trace_buf.data + i) + 1;
3436 for (i = 0; i < hldev->trace_buf.offset; i += offset) {
3437 if (*(hldev->trace_buf.data + i)) {
3439 hldev->trace_buf.data + i);
3441 hldev->trace_buf.data + i) + 1;
3445 offset = vxge_os_strlen(hldev->trace_buf.data + i) + 1;
3470 __hal_device_t *hldev = (__hal_device_t *) devh;
3472 hldev->header.debug_module_mask = mask;
3473 hldev->header.debug_level = level;
3475 hldev->d_trace_mask = 0;
3476 hldev->d_info_mask = 0;
3477 hldev->d_err_mask = 0;
3481 hldev->d_trace_mask = mask;
3485 hldev->d_info_mask = mask;
3489 hldev->d_err_mask = mask;
3509 __hal_device_t *hldev = (__hal_device_t *) devh;
3519 if (hldev->header.magic != VXGE_HAL_DEVICE_MAGIC) {
3527 status = __hal_vpath_flick_link_led(hldev,
3528 hldev->first_vp_id, port, on_off);
3557 __hal_device_t *hldev = (__hal_device_t *) devh;
3569 if (hldev->header.magic != VXGE_HAL_DEVICE_MAGIC) {
3583 if (!(hldev->vpath_assignments & mBIT(i)))
3586 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
3587 hldev->header.regh0,
3588 &hldev->vpmgmt_reg[i]->