Lines Matching refs:u_short
224 #define GLOBAL_RESET (u_short) 0x0000 /* Wait at least 1ms
226 #define WINDOW_SELECT (u_short) (0x1<<11)
227 #define START_TRANSCEIVER (u_short) (0x2<<11) /* Read ADDR_CFG reg to
233 #define RX_DISABLE (u_short) (0x3<<11) /* state disabled on
235 #define RX_ENABLE (u_short) (0x4<<11)
236 #define RX_RESET (u_short) (0x5<<11)
237 #define RX_DISCARD_TOP_PACK (u_short) (0x8<<11)
238 #define TX_ENABLE (u_short) (0x9<<11)
239 #define TX_DISABLE (u_short) (0xa<<11)
240 #define TX_RESET (u_short) (0xb<<11)
241 #define REQ_INTR (u_short) (0xc<<11)
246 #define ACK_INTR (u_short) (0x6800)
247 #define C_INTR_LATCH (u_short) (ACK_INTR|0x1)
248 #define C_CARD_FAILURE (u_short) (ACK_INTR|0x2)
249 #define C_TX_COMPLETE (u_short) (ACK_INTR|0x4)
250 #define C_TX_AVAIL (u_short) (ACK_INTR|0x8)
251 #define C_RX_COMPLETE (u_short) (ACK_INTR|0x10)
252 #define C_RX_EARLY (u_short) (ACK_INTR|0x20)
253 #define C_INT_RQD (u_short) (ACK_INTR|0x40)
254 #define C_UPD_STATS (u_short) (ACK_INTR|0x80)
255 #define SET_INTR_MASK (u_short) (0xe<<11)
256 #define SET_RD_0_MASK (u_short) (0xf<<11)
257 #define SET_RX_FILTER (u_short) (0x10<<11)
258 #define FIL_INDIVIDUAL (u_short) (0x1)
259 #define FIL_MULTICAST (u_short) (0x02)
260 #define FIL_BRDCST (u_short) (0x04)
261 #define FIL_PROMISC (u_short) (0x08)
262 #define SET_RX_EARLY_THRESH (u_short) (0x11<<11)
263 #define SET_TX_AVAIL_THRESH (u_short) (0x12<<11)
264 #define SET_TX_START_THRESH (u_short) (0x13<<11)
265 #define STATS_ENABLE (u_short) (0x15<<11)
266 #define STATS_DISABLE (u_short) (0x16<<11)
267 #define STOP_TRANSCEIVER (u_short) (0x17<<11)
287 #define S_INTR_LATCH (u_short) (0x1)
288 #define S_CARD_FAILURE (u_short) (0x2)
289 #define S_TX_COMPLETE (u_short) (0x4)
290 #define S_TX_AVAIL (u_short) (0x8)
291 #define S_RX_COMPLETE (u_short) (0x10)
292 #define S_RX_EARLY (u_short) (0x20)
293 #define S_INT_RQD (u_short) (0x40)
294 #define S_UPD_STATS (u_short) (0x80)
295 #define S_COMMAND_IN_PROGRESS (u_short) (0x1000)
327 #define ERR_INCOMPLETE (u_short) (0x8000)
328 #define ERR_RX (u_short) (0x4000)
329 #define ERR_MASK (u_short) (0x7800)
330 #define ERR_OVERRUN (u_short) (0x4000)
331 #define ERR_RUNT (u_short) (0x5800)
332 #define ERR_ALIGNMENT (u_short) (0x6000)
333 #define ERR_CRC (u_short) (0x6800)
334 #define ERR_OVERSIZE (u_short) (0x4800)
335 #define ERR_DRIBBLE (u_short) (0x1000)
403 #define FIFOS_RX_RECEIVING (u_short) 0x8000
404 #define FIFOS_RX_UNDERRUN (u_short) 0x2000
405 #define FIFOS_RX_STATUS_OVERRUN (u_short) 0x1000
406 #define FIFOS_RX_OVERRUN (u_short) 0x0800
407 #define FIFOS_TX_OVERRUN (u_short) 0x0400
421 #define RX_BYTES_MASK (u_short) (0x07ff)