Lines Matching refs:CSR_WRITE_4

353 	CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
358 CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST);
365 CSR_WRITE_4(sc, NVCTL, epic_read_eeprom(sc, EEPROM_NVCTL) & 0x1F);
714 CSR_WRITE_4(sc, COMMAND, COMMAND_TXQUEUED);
873 CSR_WRITE_4(sc, INTSTAT, status);
885 CSR_WRITE_4(sc, COMMAND, COMMAND_RXQUEUED);
954 CSR_WRITE_4(sc, COMMAND, COMMAND_TXUGO);
1050 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
1109 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
1125 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
1207 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
1269 CSR_WRITE_4(sc, GENCTL, 0);
1270 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
1279 CSR_WRITE_4(sc, GENCTL, 0);
1283 CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST);
1286 CSR_WRITE_4(sc, PRCDAR, sc->rx_addr);
1287 CSR_WRITE_4(sc, PTCDAR, sc->tx_addr);
1290 CSR_WRITE_4(sc, LAN0, ((u_int16_t *)IF_LLADDR(sc->ifp))[0]);
1291 CSR_WRITE_4(sc, LAN1, ((u_int16_t *)IF_LLADDR(sc->ifp))[1]);
1292 CSR_WRITE_4(sc, LAN2, ((u_int16_t *)IF_LLADDR(sc->ifp))[2]);
1304 CSR_WRITE_4(sc, INTMASK,
1310 CSR_WRITE_4(sc, INTSTAT, CSR_READ_4(sc, INTSTAT));
1313 CSR_WRITE_4(sc, GENCTL,
1354 CSR_WRITE_4(sc, RXCON, rxcon);
1366 CSR_WRITE_4(sc, ETXTHR, sc->tx_threshold);
1368 CSR_WRITE_4(sc, TXCON, sc->txcon);
1388 CSR_WRITE_4(sc, MC0, 0xFFFF);
1389 CSR_WRITE_4(sc, MC1, 0xFFFF);
1390 CSR_WRITE_4(sc, MC2, 0xFFFF);
1391 CSR_WRITE_4(sc, MC3, 0xFFFF);
1410 CSR_WRITE_4(sc, MC0, filter[0]);
1411 CSR_WRITE_4(sc, MC1, filter[1]);
1412 CSR_WRITE_4(sc, MC2, filter[2]);
1413 CSR_WRITE_4(sc, MC3, filter[3]);
1425 CSR_WRITE_4(sc, COMMAND, COMMAND_RXQUEUED | COMMAND_START_RX |
1439 CSR_WRITE_4(sc, COMMAND,
1527 CSR_WRITE_4(sc, COMMAND, COMMAND_STOP_TDMA | COMMAND_TXQUEUED);
1557 CSR_WRITE_4(sc, INTMASK, 0);
1558 CSR_WRITE_4(sc, GENCTL, 0);
1564 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
1568 CSR_WRITE_4(sc, GENCTL, GENCTL_POWER_DOWN);
1809 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x01));
1825 CSR_WRITE_4(sc, MIIDATA, val);
1826 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x02));