dev/ti/if_ti.c

436 		CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
466 		CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
493 		CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
561 		CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
630 		CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
686 	CSR_WRITE_4(sc, TI_WINBASE, origwin);
723 		CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr);
774 			CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval);
843 		CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr);
864 		CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr);
882 	CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd));
884 	CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
899 	CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd));
902 		CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4),
906 	CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
974 		CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx);
1864 	CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0);
1884 		CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1885 		CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1910 		CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1911 		CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1961 	CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1990 	CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
2004 		CSR_WRITE_4(sc, 0x600, 0);
2005 		CSR_WRITE_4(sc, 0x604, 0);
2006 		CSR_WRITE_4(sc, 0x600, 0x5555AAAA);
2037 	CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
2040 	CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
2086 	CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD);
2119 			CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc,
2137 	CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD |
2142 	CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA|
2157 	CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W);
2158 	CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W);
2185 	CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2188 	CSR_WRITE_4(sc, TI_GCR_GENINFO_HI,
2190 	CSR_WRITE_4(sc, TI_GCR_GENINFO_LO,
2207 	CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0);
2216 		CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0);
2218 	CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0);
2219 	CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0);
2297 	CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE);
2334 		CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
2338 		CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks);
2339 	CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks);
2340 	CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
2341 	CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds);
2342 	CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds);
2343 	CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio);
2346 	CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0);
2347 	CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2897 		CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX,
2984 	CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
3002 		CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
3187 		CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, sc->ti_tx_saved_prodidx);
3238 	CSR_WRITE_4(sc, TI_GCR_IFINDEX, device_get_unit(sc->ti_dev));
3239 	CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu +
3245 	CSR_WRITE_4(sc, TI_GCR_PAR0, (ea[0] << 8) | ea[1]);
3246 	CSR_WRITE_4(sc, TI_GCR_PAR1,
3298 	CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0);
3308 	CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
3376 		CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
3386 		CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB|
3400 		CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
3402 		CSR_WRITE_4(sc, TI_GCR_LINK, 0);
3419 		CSR_WRITE_4(sc, TI_GCR_GLINK, 0);
3420 		CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl);
3685 			CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
3690 			CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
3696 			CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS,
3702 			CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD,
3708 			CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD,
3714 			CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO,
3731 		CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type);
3929 	CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);