Lines Matching refs:onyx_write
170 onyx_write(struct onyx_softc *sc, uint8_t reg, const uint8_t value)
235 onyx_write(sc, PCM3052_REG_LEFT_ATTN, onyx_initdata.LEFT_ATTN);
236 onyx_write(sc, PCM3052_REG_RIGHT_ATTN, onyx_initdata.RIGHT_ATTN);
237 onyx_write(sc, PCM3052_REG_CONTROL, onyx_initdata.CONTROL);
238 onyx_write(sc, PCM3052_REG_DAC_CONTROL,
240 onyx_write(sc, PCM3052_REG_DAC_DEEMPH, onyx_initdata.DAC_DEEMPH);
241 onyx_write(sc, PCM3052_REG_DAC_FILTER, onyx_initdata.DAC_FILTER);
242 onyx_write(sc, PCM3052_REG_OUT_PHASE, onyx_initdata.OUT_PHASE);
243 onyx_write(sc, PCM3052_REG_ADC_CONTROL,
245 onyx_write(sc, PCM3052_REG_ADC_HPF_BP, onyx_initdata.ADC_HPF_BP);
246 onyx_write(sc, PCM3052_REG_INFO_1, onyx_initdata.INFO_1);
247 onyx_write(sc, PCM3052_REG_INFO_2, onyx_initdata.INFO_2);
248 onyx_write(sc, PCM3052_REG_INFO_3, onyx_initdata.INFO_3);
249 onyx_write(sc, PCM3052_REG_INFO_4, onyx_initdata.INFO_4);
299 onyx_write(sc, PCM3052_REG_LEFT_ATTN, l);
300 onyx_write(sc, PCM3052_REG_RIGHT_ATTN, r);