Lines Matching defs:WR4
69 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val))
225 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
226 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
408 WR4(slot, SDHCI_BUFFER, data);
422 WR4(slot, SDHCI_BUFFER, data);
694 WR4(slot, SDHCI_SIGNAL_ENABLE, 0);
866 WR4(slot, SDHCI_SIGNAL_ENABLE,
870 WR4(slot, SDHCI_ARGUMENT, cmd->arg);
888 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE);
978 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
985 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1005 WR4(slot, SDHCI_SIGNAL_ENABLE,
1232 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1235 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
1289 WR4(slot, SDHCI_INT_STATUS, intmask &
1309 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK);
1314 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK);
1321 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR);
1329 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER);
1336 WR4(slot, SDHCI_INT_STATUS, intmask);